Automotive RISC-V
2026-08-2814 min read

GigaDevice CCRC4XXX: First Post-Quantum RISC-V Automotive AI MCU — and China’s First Vehicle-Chip Standard

On August 27, 2026, the Suzhou RISC-V Automotive Ecosystem Summit launched the drafting of China’s first systematic RISC-V vehicle-control-chip standard and released a cross-industry cooperation initiative. Headlining the show was GigaDevice’s CCRC4XXX — the country’s first multi-core RISC-V automotive AI MCU with native post-quantum cryptography, ASIL-D functional safety, and an on-chip NPU for AI control loops. Full spec deep-dive below.

GigaDevice CCRC4XXX CRV6 RISC-V Post-Quantum Crypto ASIL-D Automotive MCU Vehicle Standard Suzhou Summit

The Suzhou Summit: Why This Matters

On August 27, 2026, the Open-source RISC-V Automotive Electronics Ecosystem Innovation Summit and the RISC-V Vehicle Control Chip Technical Specification Seminar convened in Suzhou. Organized by the Jiangsu RISC-V Industry Alliance and the RISC-V Open-Source Chip Industry Innovation Center, the summit drew the entire Chinese vehicle-control-chip stack: OEMs (BYD, GAC, Great Wall), Tier-1s (E-ATECK, Wuhan Lingdian, Nexsteer), IP vendors, chip vendors, base-software vendors, and toolchain vendors.

Two artifacts emerged that will shape the next decade of Chinese automotive electronics:

Eight toolchain and base-software vendors demoed live: ETAS unveiled a multi-core AUTOSAR solution on GigaDevice’s CCRC4 series (one of the smallest and fastest RISC-V OS, 6-core parallel with ultra-short interrupt response); HighTec shipped ASIL-D certified C/C++ and Rust compilers and an IDE with optimized math libraries and SDK/MCAL; IAR, SEGGER, TASKING, Neusoft Reach, Lauterbach, and Puhua Base Software each showed their respective RISC-V production paths.

GigaDevice CCRC4XXX: The Headline Chip

GigaDevice’s (Suzhou) CCRC4XXX series is the first domestic multi-core RISC-V automotive AI MCU to integrate post-quantum cryptography. It is purpose-built for software-defined vehicles (SDV) where the central SoC is being unbundled into domain controllers (body, chassis, powertrain, ADAS, cockpit) and a high-integration central domain controller — all of which need a high-performance, high-safety, RISC-V-based main controller with hardware AI acceleration.

Three product variants have entered internal testing:

Full Specifications

CCRC4XXX — Chip-Level Specifications
CPU ArchitectureCRV6 (RISC-V), 32 general-purpose + 32 floating-point registers, FPU with double-precision, hardware multiply/divide, SECDED ECC
CPU ConfigurationFlagship 6+6 heterogeneous (6 performance + 6 lock-step); mid-tier 4+2
CPU ClockUp to 500 MHz
ComputeUp to 10,500 DMIPS; CRV6 single-core efficiency surpasses TriCore and ARMv8-R
AI Engine (NPU)On-chip, up to 0.3 TOPS @ INT8, dedicated neural-network operators
ProcessTSMC 22 nm RRAM (replaces eFlash; higher density, lower power, faster read/write, simultaneous read/write for faster OTA)
Code NVM24 MB RRAM
Data NVM2 MB RRAM
SRAM9 MB on-chip
External StoragePSRAM, eMMC
Functional SafetyISO 26262 ASIL-D (highest)
ReliabilityAEC-Q100 Grade 1
Info SecurityEnhanced HSM, Evita-Full (highest), native Post-Quantum Cryptography (PQC) co-processor
VirtualizationHS / VS / VU three-level privilege; multi-PMP and sMPU hardware virtualization; multi-OS isolation
CryptographyRSA / ECC / SM2 / SM3 / SM4 + PQC (ML-KEM, ML-DSA) — triple-fused algorithm support
Operating Temperature-40 °C to +125 °C (Grade 1)
PackageBGA-416, BGA-680 (multiple)
CCRC4XXX — Connectivity / I/O
CAN-FD20 channels (gateway + routing)
LIN28 channels
DSPI15 channels
QSPI2 channels
Ethernet2× Gigabit Ethernet with TSN (Time-Sensitive Networking)
SENT12 + 13 channels (sensor peripheral interface)
PSI54 channels (sensor peripheral)
OtherComplete analog front-end including GTM4.1 timer, SAR ADC, and high-precision analog interfaces
Total Effective I/OUp to 570 pins
Hardware Acceleration
CGDMAHardware data-routing engine — CAN-to-CAN, CAN-to-Memory, CAN-to-Ethernet, Ethernet-to-Ethernet forwarding with zero CPU intervention
GTM4.1Generic Timer Module 4.1 for complex PWM and motor-control timing
AI NPU0.3 TOPS INT8, embedded in the MCU die — AI-in-Chip for local inference at the edge of every domain

Why Post-Quantum Crypto (PQC) on a Vehicle MCU?

Modern connected vehicles have a 10–15 year service life. Quantum computers capable of breaking RSA-2048 and ECC-256 are widely forecast to arrive within that window. A vehicle sold in 2026 will still be on the road in 2041 — well within reach of a cryptographically-relevant quantum computer. Hardcoding today’s classical algorithms means that a car delivered next year is already a time-bomb for harvest-now-decrypt-later attacks.

The CCRC4XXX takes a pragmatic three-track strategy rather than a PQC-only pivot:

The hardware crypto module is Evita-Full (the highest level in the Evita automotive HSM specification). It supports hybrid operation — the same TLS handshake can carry classical and PQC signatures in parallel, so vehicles can roll out PQC support incrementally via OTA firmware updates without touching the silicon. That’s critical because the OEM’s fleet-inventory lifetime vastly exceeds the cryptographic-policy lifetime.

Six Architectural Innovations

  1. Native AI in the MCU. The 0.3 TOPS INT8 NPU lives on the same die as the CPU cores. Perception, prediction, and diagnostic workloads run inside the MCU without off-chip AI accelerators — moving AI compute from central SoCs to the edge of every domain controller.
  2. CGDMA hardware data routing. Software-defined vehicles have thousands of sensors and dozens of ECUs. The CGDMA engine forwards CAN-to-CAN, CAN-to-Memory, CAN-to-Ethernet, and Ethernet-to-Ethernet in hardware, with no CPU cycles burned — a major latency and determinism win for multi-domain SDV architectures.
  3. Multi-mode hardware virtualization. The CRV6 core supports HS (hypervisor) / VS (supervisor) / VU (user) three-level privilege with multi-PMP and sMPU. Multiple isolated OS instances (e.g., instrument-cluster RTOS + ADAS Linux) can share one CCRC4XXX without mutual interference, enabling the “one chip, many domains” consolidation that SDV demands.
  4. Storage and I/O abundance. 24 MB code RRAM + 2 MB data RRAM + 9 MB SRAM, expandable via eMMC and PSRAM. Twenty CAN-FD, twenty-eight LIN, fifteen DSPI, two QSPI, two Gigabit Ethernet with TSN, twelve-plus-thirteen SENT, and four PSI5 give a single chip enough I/O to act as a standalone central-domain controller — no companion MCU needed.
  5. Open RISC-V ecosystem. RISC-V removes ISA licensing fees and royalty overhangs. Toolchain support includes IAR, Green Hills, HighTec, TASKING, and GCC; debuggers from Lauterbach, iSYSTEM, and SEGGER; base software from EB tresos, Vector, ETAS, Puhua, Neusoft Reach, and Siemens — giving OEMs and Tier-1s a full vendor-neutral tool stack and dramatically reducing vendor lock-in.
  6. Vehicle-grade security. Evita-Full HSM with PQC, classical, and Chinese-national-cryptography triple fusion — one of the few domestic automotive MCUs to ship all three.

Software Base — AUTOSAR and Beyond

The CCRC4XXX supports AUTOSAR 4.4.0 standard MCAL, with adapter packs for EB tresos, Vector, ETAS, Puhua, Neusoft Reach, and Siemens. This means OEMs and Tier-1s can drop the CCRC4XXX into an existing E/E architecture and keep their current application-layer software, dramatically shortening the SDV migration curve.

Application notes already published cover:

CRV6 RISC-V Core — What’s Inside

The CRV6 is GigaDevice’s in-house RISC-V core. Per the chip documentation, it surpasses TriCore and ARMv8-R in single-core efficiency. Architectural details released at the summit:

The 6+6 heterogeneous configuration pairs six performance cores with six lock-step cores — the lock-step cores run identical instructions in lock-step with the performance cores and compare results cycle-by-cycle, achieving ASIL-D fault coverage without external lock-step MCUs.

Toolchain Stack — Verified Vendor Support

LayerVendors Demonstrated at Suzhou Summit
Compilers / IDEHighTec (ASIL-D C/C++/Rust, IDE), IAR, TASKING, GCC
Debuggers / TraceLauterbach (TRACE32), SEGGER (J-Link)
RTOS / HypervisorETAS (RISC-V OS, 6-core parallel, ultra-short interrupt response)
AUTOSAR MCAL / RUCVector, EB tresos, ETAS, Puhua, Neusoft Reach, Siemens
Modeling / DevOpsDaVinci (Vector), EB tresos Studio, ETAS ASCET
Functional SafetyHighTec (ASIL-D), SGS-TÜV (certification)

Code Sample — CCRC4XXX Bring-Up (RTOS Stub)

A minimal boot stub for the CCRC4XXX, illustrating the lock-step mode configuration and CGDMA hookup for CAN routing. Real OEM stacks vary, but the pattern below shows the platform’s register layout and configuration knobs.

/* CCRC4XXX minimal bring-up stub (illustrative, not from datasheet) */
#include <ccrc4xxx.h>

void SystemInit(void) {
    /* Switch to PLL @ 500 MHz on CRV6 P-core cluster */
    CGU.CLK_CTL = CGU_SRC_PLL | CGU_PLL_FBDIV_50 | CGU_PLL_REFDIV_1;
    while (!(CGU.STATUS & CGU_PLL_LOCKED));

    /* Enable lock-step pairing on P-cores 1..5 with cores 6..11 */
    SAFETY.LS_CONFIG = LS_PAIR_EN(0x3F);
    while (!(SAFETY.LS_STATUS & LS_PAIRED));

    /* CGDMA: route CAN0 -> CAN5 with deterministic latency */
    CGDMA.CH[0].SRC   = DMA_SRC_CAN0_RX;
    CGDMA.CH[0].DST   = DMA_DST_CAN5_TX;
    CGDMA.CH[0].CTRL  = DMA_ZERO_CPU | DMA_TS_EN;
    CGDMA.CH[0].PRID = 7;          /* highest priority */
    CGDMA.CH[0].ENABLE = 1;

    /* HSM: enable ML-KEM and ML-DSA alongside classical + SM */
    HSM.ALG_ENABLE = HSM_RSA | HSM_ECC | HSM_SM2 | HSM_SM3 | HSM_SM4
                   | HSM_ML_KEM | HSM_ML_DSA;
    HSM.MODE = HSM_EVITA_FULL;
}

/* Application entry */
int main(void) {
    SystemInit();
    Rtos_Start();      /* ETAS RISC-V OS or AUTOSAR RUC */
    return 0;
}

Strategic Significance — Three Layers

  1. Domestic high-end automotive MCU — directly displaces foreign incumbents (Infineon TC4Dx, Renesas U2A16 / U2B24) in body, chassis, powertrain, and central-domain controllers. Compatible interface count and higher compute.
  2. SDV hardware base — open architecture + virtualization + on-chip AI + high-bandwidth TSN Ethernet — the substrate that SOA, multi-domain fusion, and cloud-native vehicle services need.
  3. RISC-V automotive ecosystem — closes the loop with tools, base software, OEMs, and Tier-1s. Combined with the new RISC-V Vehicle Control Chip Technical Specification, this is the moment Chinese RISC-V automotive chips go from prototype to policy-backed mass production.

Comparison — Domestic vs. International High-End Automotive MCUs

ParameterGigaDevice CCRC4XXXInfineon TC4DxRenesas U2A16 / U2B24
ArchitectureRISC-V (CRV6)TriCoreRH850 / Arm
Compute (DMIPS)10,500 (flagship)~5,000 (similar tier)~6,000 (similar tier)
SRAM9 MB~4 MB~3 MB
CAN-FD20 channels12 channels10 channels
Gigabit Ethernet (TSN)2 ports1 port1 port
On-chip AI0.3 TOPS NPUNoneNone
Post-Quantum CryptoNative (ML-KEM, ML-DSA)NoneNone
Functional SafetyASIL-DASIL-DASIL-D
Open ISAYes (RISC-V)No (proprietary)No (proprietary)
Open ToolchainHighTec, IAR, GCC, TASKINGTasking, Green HillsGreh, IAR

Outlook

The Suzhou summit marks the moment that Chinese RISC-V automotive electronics transitioned from a collection of pilots to a coordinated, standard-backed ecosystem. Three signals to watch in the next 12 months:

Official Resources

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