WCH MCU
2026-08-2210 min read

CH32X035: WCH's All-in-One USB + Type-C PD RISC-V MCU

WCH's CH32X035 drops the external PD trigger chip. Built on the QingKe V4C RV32IMAC core, it integrates USB 2.0 full-speed, USB PD and Type-C PHYs, plus a programmable I/O controller, dual OPA, triple CMP, 12-bit ADC and 65 KB Flash — all in one 2-to-5.5 V industrial-grade package as small as QFN12.

CH32X035 WCH QingKe V4C RV32IMAC USB PD Type-C PIOC Power Delivery

Overview

The CH32X035 is WCH's USB + Type-C PD microcontroller built around the 48 MHz QingKe V4C RISC-V core (RV32IMAC). Unlike the older CH32V003 (a tiny 48 MHz RV32EC part with no USB), the X035 is a different species: the protocol stack, the BMC physical layer and the Type-C termination are all built into the silicon, so you can negotiate 5 V / 9 V / 12 V / 15 V / 20 V PDOs without an external IP2721 or CH224K trigger chip.

The integrated USB 2.0 full-speed controller/PHY runs as both Host and Device, the I/O counts go up (24 external interrupts, four USARTs, two 16-bit advanced timers + general-purpose/watchdog/SysTick timers, an 8-channel DMA), and the analog side gains a second OPA and third comparator plus a 12-bit ADC — the typical mix for a programmable buck/boost source or a Sink that needs current/voltage monitoring.

Key Specifications

CoreQingKe V4C, RV32IMAC, single-cycle hardware mul + hardware div
Max Frequency48 MHz
Flash / SRAM65 KB Flash / 20 KB SRAM
Supply Voltage2.0 – 5.5 V (wide-voltage, 3.3 V / 5 V ready)
USBUSB 2.0 full-speed Host + Device controller & PHY
USB PDUSB PD 3.0 controller + Type-C BMC PHY (built-in, no external trigger IC)
Debug2-wire SDI (serial debug interface)
Unique ID96-bit factory-programmed chip ID
Low-Power ModesSleep / Stop / Standby
ResetPower-on reset, brownout reset (BOR/LVD/LVR/LVI), programmable voltage monitor
Package OptionsLQFP64M, LQFP48, QFN28, QSOP28, QFN20, TSSOP20, QFN12

Peripherals at a Glance

Programmable I/OPIOC (WCH's PIO-style programmable protocol I/O controller)
DMA8-channel general-purpose DMA
Analog2× OPA/PGA, 3× voltage comparator (CMP), 12-bit ADC (multi-channel)
Touch14-channel TouchKey
Timers2× 16-bit advanced, 1× 16-bit general, 2× watchdog (IWDG/WWDG), 1× SysTick
Communication4× USART (LIN, ISO7816), 1× I2C (SMBus / PMBus), 1× SPI
GPIOFast GPIO with 24 external interrupts, 5 V-tolerant

Why Built-In PD Matters

The classical "MCU + external trigger IC" topology — an MCU plus an IP2721, CH224K, HUSB238 or FUSB302 — works but adds:

The CH32X035 moves PD to the metal: the BMC encoding/decoding on CC1/CC2, the message CRC, the Source-Capabilities / Request / Accept / PS_RDY state machine and the Type-C attach/detach detection all live in the silicon. Your firmware only deals with policy ("what voltage did the partner offer, what do I want, what role am I").

Walking Through the Official Sink Example

WCH ships an EVT/EXAM/USBPD directory inside the CH32X035EVT.ZIP evaluation bundle. The Sink example (USBPD_SNK) is the smallest useful end-to-end demo. The high-level flow is:

// 1. Initialise USB PD stack (BMC PHY, protocol timers, Source-Cap detection)
USBPD_Init();

// 2. Wait for a Source to publish its capabilities
while (USBPD_GetRxStatus() == RX_EMPTY) { __WFI(); }

// 3. Parse the partner's Source_Capabilities PDO array
PDO_Source_Capabilities_t srcCap;
USBPD_GetMessage(USBPD_MSG_SRC_CAP, &srcCap);

// 4. Pick a 20 V (100 W) PDO and request it
uint8_t objPos = 3;                 // index of the 20 V PDO
RDO_Request_DataObject rdo = {
    .objectPosition   = objPos,
    .giveBackFlag     = 0,
    .capabilityMismatch = 0,
    .usbCommunicationCapable = 0,
    .noUsbSuspendFlag = 1,
    .operatingCurrent = 3000 / 10,  // 3.0 A in 10 mA units
    .maxOperatingCurrent = 5000 / 10
};
USBPD_SendRequest(USBPD_MSG_REQUEST, &rdo);

// 5. Wait for Accept, then PS_RDY, then enable your downstream rail
if (USBPD_WaitForMsg(USBPD_MSG_ACCEPT) &&
    USBPD_WaitForMsg(USBPD_MSG_PS_RDY)) {
    GPIO_SetBits(GPIOA, GPIO_Pin_0);   // turn on downstream regulator EN
}

The board-side hardware hook-up only needs:

PIOC — the PIO-Style State Machine

The X035 introduces the PIOC (Programmable I/O Controller), WCH's RP2040-PIO-style peripheral that runs a small microprogram on dedicated logic to bit-bang or protocol-manipulate pins independently of the CPU. That means you can keep CC BMC, UART, SPI, I²C, even custom LED/IR protocols pumping at deterministic timing while the main core does application work — useful when you are also monitoring OPA outputs or driving PDOs.

Analog Toolkit for Programmable Power

The 2× OPA/PGA + 3× CMP + 12-bit ADC are purpose-built for the typical monitoring loop a programmable source needs:

What the Official EVT Pack Includes

All projects target MounRiver Studio (MRS), WCH's Eclipse-based IDE with the GCC RISC-V toolchain pre-bundled.

When to Pick the CH32X035

Compared with the older CH32V003, the X035 trades the ultra-low-cost RV32EC core for a fully-equipped RV32IMAC part with hardware mul/div, four USARTs, 65 KB Flash, and a full USB-PD + Type-C stack on-die. Where it fits best:

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