中科通量金刚GC3: RISC-V + Dataflow Architecture for Video AIGC
A new RISC-V-based dataflow architecture chip from 中科通量 (SinoDataFlow) targets the exploding video AI market — 12 RISC-V cores, 200 TOPS INT8, 128GB unified memory, and a radically different approach to compute that eliminates data搬运 bottlenecks.
The Problem: Video AI Hits the GPU Ceiling
Video generation has become the hottest AI battleground of 2026. With Seedance 2.5, MiniMax H3, and other models pushing the boundaries of text-to-video and image-to-video, the demand for inference compute is exploding. But there's a fundamental problem: general-purpose GPUs waste enormous amounts of energy and time on data搬运 — moving data between memory and compute units.
According to 中科通量 CTO 吴冬冬 (Wu Dongdong), the bottleneck in video AI is not raw compute power, but data movement overhead. In video understanding (surveillance, quality inspection, content moderation), every frame must travel between memory and the GPU, creating latency at scale. In video generation, model parameters often exceed 100GB, and repeated read-write cycles burn bandwidth and power.
"搬运少了，Token就便宜了。" — 吴冬冬, CTO of 中科通量
金刚GC3 Key Specifications
| Chip Name | 金刚GC3 (King Kong GC3) |
| Manufacturer | 中科通量 (SinoDataFlow) |
| Architecture | Dataflow compute + RISC-V control plane |
| RISC-V Cores | 12 cores (control plane / scheduling) |
| AI Compute (INT8) | 200 TOPS |
| Memory | 128GB LPDDR5 ECC Unified Memory |
| Video Decode | 128 channels @ 1080P |
| Video Encode (reconfigurable) | 8K @ 120fps |
| Compute Utilization | 80–90% (vs. typical GPU ~50–60%) |
| Target Workloads | Video generation, video understanding, multi-modal AI |
| OS Support | Kylin, openEuler, OpenHarmony, Linux |
| Ecosystem | Open-source software stack, OpenAtom Foundation platinum donor |
Dataflow vs. Control Flow: A Paradigm Shift
The GC3's most radical design choice is its dataflow architecture, which fundamentally differs from the von Neumann (control flow) model used by virtually all CPUs and GPUs:
| Dimension | Control Flow (CPU/GPU) | Dataflow (GC3) |
|---|---|---|
| Execution Model | Program counter fetches instructions sequentially | No program counter; ops execute when input data is ready |
| Parallelism | Limited by instruction window size | All ready ops execute simultaneously |
| Memory Access | Intermediate results repeatedly read/written | Results flow directly between compute nodes |
| Synchronization | Barrier mechanisms needed across cores | Natural data-dependency ordering, no global barriers |
| Silicon Overhead | Branch prediction, register renaming, etc. | Simpler logic, less area, lower power |
Think of it like a factory assembly line: in control flow, a central dispatcher tells each station when to start; in dataflow, each station starts automatically the moment its parts arrive. The result is near-zero idle time and dramatically reduced memory traffic.
Why This Matters for Video AI
Video workloads are characterized by massive parallelism, regular compute patterns, and enormous data volumes — precisely the conditions where dataflow architecture excels. Video generation involves pixel-level and matrix-level computations that can all execute in parallel once their inputs are ready, without being bottlenecked by an instruction window.
RISC-V's Role: The Control Plane
The 12 RISC-V cores in the GC3 serve as the control plane — they do not perform heavy computation themselves, but instead orchestrate and configure the dataflow compute units. This is a critical design decision:
- Reconfigurability: The same hardware can be reconfigured for different workloads. The 128-channel 1080P decoder can be reorganized into an 8K@120fps encoder when switching from video understanding to video generation.
- Software-defined hardware: As AI models iterate every 3 months, rigid ASIC designs risk obsolescence. The RISC-V cores provide scheduling flexibility — stable operators (like matrix multiply) are hardened into efficient NPU units, while variable parts are handled by the compiler and CPU.
- Open instruction set: RISC-V's open, free, and customizable nature enables instruction-level sovereignty and hardware-software co-optimization specific to video intelligence scenarios.
Unified Memory: One Chip, No搬运
The GC3's 128GB LPDDR5 ECC unified memory is a game-changer for video generation. Traditional GPU setups often require multi-card communication to hold large model parameters and intermediate activations, with each cross-card transfer adding latency and power consumption.
With 128GB on a single chip, the GC3 can hold an entire large video generation model in one unified address space. Data flows between compute units without copy operations — addresses are passed, not data. This eliminates the most expensive bottleneck in video AI inference.
Software Ecosystem and OS Support
中科通量 has invested heavily in ecosystem building:
- Toolchain: Compiler and development tools are available and being continuously improved.
- Open source: The software stack has been open-sourced, with an active developer community.
- OS compatibility: As an OpenAtom Foundation platinum donor, the company has ensured that Kylin (麒麟), openEuler (欧拉), and OpenHarmony (鸿蒙) can all run natively on the GC3.
- Cloud-edge deployment: Cloud-side for high-density AI data centers serving operators and platform companies; edge-side via AI PCs and the "Little King Kong" (小金刚) compute box, initially targeting research scenarios.
Commercial Roadmap
The GC3 follows a cloud-edge-end deployment strategy:
- Cloud: High-density AI compute centers providing cost-effective video Token services for telecom operators and large platforms. Also enables private Token service platforms for enterprises and industrial parks.
- Edge: AI PCs and the 小金刚 (Little King Kong) smart compute box, initially focused on academic research users who are more willing to adopt new technology and provide feedback.
Beyond Video: Multi-Modal Ambitions
While video remains the "basic盘" (core business), 吴冬冬 sees the GC3's capabilities extending further. As chip capabilities improve, language models and multi-modal applications are entering the GC3's capability radius. "Images and language together — that's how humans understand the world, and all of this we can reach," he said.
This aligns with McKinsey's prediction that by 2030, AI accelerators with dedicated ASICs will handle the majority of AI workloads — a shift from one-size-fits-all GPUs to specialized architectures tailored to specific data patterns.
Industry Context
The GC3 arrives at a pivotal moment for the RISC-V ecosystem. In 2026, the RISC-V industry is widely seen as reaching a "watershed" — transitioning from technical validation to scaled commercialization. The RVA23 Profile and Server Platform Specification 1.0 are now landing, providing unified hardware-software interfaces across vendors. Linux 7.2 has raised the RISC-V default core limit from 64 to 256, officially opening the server era.
The dataflow + RISC-V combination represents one of the most innovative architectural approaches in this transition — not just adopting RISC-V as an instruction set, but rethinking the entire compute paradigm around it.