Lingxu Smart P100: China's First Dynamic SMT4 RISC-V Server CPU, Built for Agentic AI

P100 is the first domestic dynamic SMT4 server-grade RISC-V CPU core: SMT1→SMT4 runtime switching with zero reboot, 20+ stage out-of-order pipeline, 8-decode / 10-issue superwide, TAGE branch prediction, >20/GHz single-core (SPEC CPU2006), hardware RAS auto-recovery. Test chip taped out Aug 2026 on a domestic advanced node; 128-core CPU 2027, mass production 2028.

Lingxu Smart P100 SMT4 Agentic AI Out-of-Order RISC-V Server Domestic Foundry

Why a New Chinese RISC-V Server CPU Now

In the agentic-AI era, Intel/Georgia Tech joint research shows CPU execution accounts for 50% to 90.6% of total inference time — task decomposition, sandbox lifecycle, context memory, tool calls, multi-agent coordination all live on the host CPU. Morgan Stanley projects the agentic-driven CPU market to reach USD 32.5–60 billion by 2031, roughly half of the entire CPU market. CPU:GPU core ratios are shifting from 1:4 to 1:1 or higher.

Lingxu Smart (灵睿智芯) is a Shenzhen-headquartered startup founded in 2024. The P100 project kicked off in late April 2026; the test chip entered tape-out at a domestic advanced node in late August 2026 — a four-month cycle from kickoff to silicon, less than half of the industry average. The leadership team is staffed with veterans from IBM Power; CTO 苟鹏飞 spent ten-plus years on IBM's Power processor line before moving to Lingxu.

P100 Microarchitecture at a Glance

Parameter	Specification
ISA	RV64 RISC-V (open instruction set, vendor-custom extension interface)
Pipeline	20+ stage deep out-of-order superscalar
Issue Width	8-decode / 10-issue superwide
Branch Prediction	Advanced TAGE with deep history tables
Threading	Dynamic SMT4 (SMT1 ↔ SMT4 live switching, no reboot)
Single-core Performance	>20 / GHz (SPEC CPU2006)
RAS	End-to-end error detect + hardware isolation + auto-replay
Extension Interface	RISC-V custom instruction slot for in-core acceleration
Roadmap	Test chip: Aug 2026 (taped out); 128-core CPU: 2027; Mass production: 2028

The headline differentiator is the >20-stage deep pipeline. On a domestic process node, reaching high clock speed is harder than on TSMC 3–5 nm; going deeper buys back frequency headroom that a 12–14 stage mainstream core cannot reach on the same node. For agentic workloads whose latency budget is dominated by serial decision chains (often hundreds to thousands of steps), every nanosecond of clock speed matters.

Dynamic SMT4: The Engineering Moat

SMT (Simultaneous Multithreading) is a well-understood textbook technique — Intel has shipped SMT2 since 2002 on every consumer CPU, IBM has shipped SMT8 on Power10. The engineering challenge is correctness at scale:

Thread resource scheduling: physical registers, queue entries, cache ports, execution units, fetch/decode/issue bandwidth must all be partitioned and arbitrated per cycle.
State isolation: speculative state, traps, interrupts, debug state, exception frames must remain fully isolated between threads.
Error containment: a transient fault in one thread must not corrupt another; recovery must be per-thread, not per-core.

Dynamic SMT4 goes one step further — the OS can request SMT1 / SMT2 / SMT4 modes, and the hardware migrates threads live between modes with no OS reboot. Each mode re-partitions the core: SMT1 dedicates full bandwidth to one thread, SMT4 time-slices four threads across the same physical resources.

This matters for agentic AI because real workloads are mixed:

Compute-dense moments: tight GPU-side prefill/postfill coordination, or large-context KV cache management — the OS flips the relevant cores to SMT1 to maximize single-thread speed.
I/O-dense moments: hundreds of waiting tool calls, sandbox pids, file/network/memory I/O — the OS flips cores to SMT4 to maximize throughput on the blocking tasks.
Heterogeneous moments: supervisor + scheduler + executor agents running concurrently — SMT2 or SMT3 often hits the best perf/W.

According to CTO 苟鹏飞, the dynamic SMT4 design is at least three years ahead of domestic peers — most Chinese CPU teams are still wrestling with stable SMT2. NVIDIA's Vera agentic CPU (announced earlier in 2026) only reaches SMT2.

Workload Modelling — Why Agentic AI Excuses the Cost

Conventional wisdom says SMT adds little to well-vectorized HPC and throughput AI, where the GPU does 90%+ of the work. But agentic AI inverts that model. Three observations:

Per-token cost is dominated by control flow. With tokens at $0.001–0.01 on commodity GPUs, the marginal cost of a 100–500 ms CPU stall (from a missed branch, a cache miss, a syscall) outweighs the marginal compute cost. SMT4 hides the stall by switching threads.
Tool-call pipelines are bursty. One agent decision spawns dozens of tool subprocesses — the dataflow is wide at the I/O layer, narrow at the reasoning layer. SMT4 keeps the I/O layer saturated while a single SMT1 thread powers the reasoning layer.
Multi-agent scheduling is fundamentally pre-emptive. Tens of agents share the host CPU; each runs in short bursts with frequent context switches. SMT minimizes the context-switch overhead per agent.

Hardware RAS: Auto-Recovery Built for Long-Running Agents

Agent chains run unattended for hours, sometimes days. A transient SEU (single-event upset) on one agent must not propagate down the decision chain. P100 layers three defenses:

End-to-end error detection — pipeline parity and ECC on all queues, register files, caches; no silent corruption.
Hardware error isolation — on detection, the offending thread is fenced; other threads continue with no observable impact.
Hardware auto-replay — the failed instruction stream is replayed from the faulting point; from the user-VM's perspective, the thread simply continues. CTO 苟鹏飞 calls this the "软件层面完全无感" property — business-visible SLA is preserved even under soft-error events.

This is a different design point from the mainstream desktop/server RAS posture (which detects, logs, and signals the OS). For long-horizon agentic workloads, the right behavior is resume, not report.

RISC-V Custom Extension Slot — Co-Designed Acceleration

P100 exposes a vendor-custom instruction slot inside the pipeline. Customers can integrate domain-specific acceleration directly into a P100 core — DPU network processing, embodied-robot motor control, ADAS perception pre/post-processing, AI-accelerator sideband logic. The general-purpose scalar + vector + custom accelerator all share one hart context, so there's no need for a separate accelerator ISA, driver stack, or memory-coherency fence.

This is RISC-V's biggest long-term advantage over x86 and ARM: the spec explicitly carves out reserved encoding space for vendor extensions. P100 is among the first domestic cores to expose this seam inside the front end, not behind an MMIO device.

Domestic Supply-Chain Strategy

COO 徐越 frames the supply-chain commitment succinctly: downstream customers demand full domestic provenance, and geopolitical risk makes overseas foundry tape-out unreliable. P100 is therefore tied to a domestic advanced process node from day one. Lingxu positioned to be on the design-tools critical path with the foundry, so they can influence PDK tuning rather than just consume it.

AI tools are also deployed aggressively through the design phase — reportedly RMB 1,000 / engineer / month in AI tool spend covering code generation, formal verification, coverage analysis, assertion generation, and physical-design early-stage iterations. This is one of the mechanisms compressing the four-month kickoff-to-tape-out cycle.

Productization Roadmap

2026-08: P100 single-core test chip taped out on domestic advanced node.
2026–2027: Validation, frequency/PV characterization, RAS verification, inter-core coherence bring-up.
2027 (planned): 128-core server-class SoC tape-out. Coherent mesh interconnect, multi-socket SMP.
2028 (planned): Volume production.
Adjacent IP licensing: selectively, targeting DPU, ADAS, embodied-robot, AI accelerator scenarios — never to direct general-purpose CPU competitors.

CPU + GPU Co-design with Biren and Domestic GPU Vendors

Most notably, Biren (壁仞) and other domestic GPU vendors participated in the Pre-A round. The two teams are co-optimizing the CPU/GPU compute ratio and the unified scheduler — framing it as "国产智能体算力一体机" (a domestic agentic-AI compute appliance). The intent is to eliminate the "大脑快、手脚慢" (brain fast, hands slow) mismatch where the host CPU cannot keep the domestic GPU fed.

Position in the Domestic RISC-V Server Field

	Lingxu P100 (RISC-V)	SiFive P870-D (RISC-V)	SpacemiT K3 (RISC-V)	NVIDIA Vera (Arm)
Core Architecture	RISC-V RV64	RISC-V RV64	RISC-V RV64	Arm v9.x custom
Pipeline Depth	20+ OoO stages	13 OoO stages (sequential)	10-stage superscalar	12+ OoO stages
Issue Width	8-decode / 10-issue	3-issue	3-issue	5-issue
SMT	Dynamic SMT4	SMT2	No SMT	SMT2
Target	Agentic AI host CPU	Datacenter general-purpose	Edge AI / gateway	NVIDIA GB200/GB300 rack host
Foundry	Domestic advanced node	TSMC 3 nm	TSMC 5 nm	TSMC 3 nm
Single-core SPEC INT	>20 / GHz	>12 / GHz (estimated)	~9 / GHz (estimated)	~22 / GHz (estimated)
Status	Test chip 2026, MP 2028	Production silicon (BigSky)	Mass production	Pre-production

P100's deepest differentiation is the dynamic SMT4 — on raw single-thread throughput the domestic production node will lag the leading-edge nodes (process gap), but on multi-thread agentic throughput (where SMT4 keeps the tool-call pipeline full), the architectural lead is unambiguous. This trades well against the realities of domestic foundry availability.

What This Means for the Wider RISC-V Ecosystem

First credible domestic server-class CPU core: prior domestic RISC-V cores were largely embedded/edge-class. P100 is the first to credibly target multi-socket server workloads.
Dynamic SMT as a domestic capability: SMT2/4 has long been assumed to be “Big Iron” territory (Intel, IBM, AMD). P100 surfaces it as a domestic engineering competency.
RISC-V custom extension becomes a product lever: the in-core extension slot positions RISC-V as the right substrate for heterogeneous CPU+accelerator SoCs — exactly the architecture agentic AI demands.
Aggressive design cadence as a model: four-month design cycle is unrealistic for most established vendors but acceptable for a focused startup. The AI-augmented design flow is increasingly the differentiator.

Limitations and Open Questions

Process gap: Domestic advanced node will likely run 0.5–1.0 GHz below TSMC's leading edge at the same time. The deeper pipeline partially compensates, but absolute frequency will likely trail.
Software maturity: Dynamic SMT raises the bar for OS scheduler, debugger, profiler, and performance-counter support. Linux mainline has stable SMT2 hotpath support; SMT4 needs explicit upstream contributions.
Coherent mesh / inter-core interconnect is not yet validated; the 128-core 2027 tape-out will be the first proof point.
Independent verification: Public silicon-photography, benchmark-per-GHz, and SPEC submission are not yet available.
2028 mass-production target depends on domestic advanced-node yield ramps — a known industry risk.

Bottom Line

Lingxu Smart P100 reframes RISC-V server CPU design for the agentic-AI era: dynamic SMT4 for mixed workload bursts, deep OoO pipeline to compensate for domestic node frequency headroom, hardware RAS auto-recovery for long-horizon agent chains, and an in-core custom-extension slot for heterogeneous CPU+accelerator SoCs. The test chip is on silicon; the real questions are at the 128-core SoC level in 2027. Whoever wins the domestic agentic-AI CPU slot in 2028 may set the pace of the broader Chinese CPU industry through the end of the decade.