RISC-V Server Chips Enter Production Datacenter: LX500, K3 & JH-B100
RISC-V server silicon is moving from lab to production racks. We look at three chips from the 5th Dishui Lake China RISC-V Industry Forum and the July 2026 Hefei production line that target the data center from compute, AI acceleration, and board-management angles.
Overview
For years the knock on RISC-V was "great for MCUs, not ready for the server room." That changed in 2026. The combination of the RVA23 profile ratified in October 2024 and the RISC-V Server Platform Specification 1.0 published at the RISC-V Summit Europe 2026 gave hardware and OS vendors a single contract to build against. The result is now visible in production silicon: a RISC-V+AI server CPU, an RVA23 application processor, and a RISC-V server-management BMC chip have all entered production or mass-production qualification.
This article examines three representative parts:
- BlueChip LX500 — the first mass-produced RISC-V+AI server CPU, with an integrated 75 TOPS NPU and CXL 2.0 memory expansion.
- SpacemiT K3 — the first RVA23-compliant mass-production RISC-V AI CPU, already covered in depth but now appearing in server form factors.
- StarFive JH-B100 — the first RISC-V architecture server BMC/management chip.
Together these three devices cover compute, AI inference, and platform management — the minimum set needed for a credible rack-mounted RISC-V server.
Why 2026 Became the Server Year
Two standards events set the table. First, the RVA23 profile froze in October 2024 and added vector, hypervisor, scalar crypto, and cache-management extensions to the 64-bit application-processor baseline. Second, the RISC-V Server Platform Specification 1.0 was ratified at RISC-V Summit Europe 2026 in Bologna. As RISC-V International CEO Andrea Gallo stated, the release completed the chain from "RVA23 profile, to server SoC, to server platform."
With a platform spec in place, Linux distributions and firmware developers could target one behavior model instead of one per vendor. Ubuntu 26.04 LTS shipped with native RVA23 support, and Canonical is moving the riscv64 baseline to RVA23 from Ubuntu 25.10 onward. The software-firmware-hardware contract now exists.
BlueChip LX500: CPU + AI in One Socket
In July 2026, a Hefei production line produced the first batch of LX500-powered rack servers. The LX500 is described as the world's first mass-produced RISC-V+AI server CPU. Instead of the traditional "CPU + discrete PCIe accelerator" split, it integrates general-purpose RISC-V cores and an AI engine on the same die, sharing memory.
| Attribute | Value / Feature |
|---|---|
| Architecture | 48-core heterogeneous RISC-V CPU |
| CPU cores | 32 performance cores + 16 efficiency cores |
| AI compute | 75 TOPS INT8 integrated NPU |
| Memory | DDR5 with CXL 2.0 expansion, up to 2 TB |
| Interconnect | On-die unified memory between CPU and NPU |
| Target | AI inference, cloud computing, high-performance computing |
| Status | Mass production (July 2026, Hefei) |
The unified-memory approach removes the repeated host-to-device copies that bottleneck CPU+GPU or CPU+NPU split architectures. For inference workloads that fit in the 2 TB address space, this can mean lower latency and simpler software: a single process space, no CUDA-style memory management, and no PCIe DMA bookkeeping.
SpacemiT K3: The RVA23 Reference in Server Form Factors
SpacemiT's K3 has already been covered as an AI CPU and robotics chip, but its server credentials are worth restating. It is the first mass-production chip to comply with the RVA23 profile, which makes it a natural reference for server boards.
| Attribute | Value / Feature |
|---|---|
| CPU cores | 8x X100 @ 2.4 GHz, 4-issue out-of-order |
| AI cores | 8x A100, 60 TOPS INT8 |
| General compute | 130 KDMIPS |
| Memory | LPDDR5 up to 32 GB, 51 GB/s |
| PCIe | 8 lanes Gen3 |
| Ethernet | 4x GMAC with TSN |
| RVA23 compliance | Yes — first mass-production RVA23 chip |
| Server products | K3 Pico-ITX, CoM260 module, server boards |
K3 is not a traditional server CPU on the scale of LX500, but it is already used in edge-server and compact-rack products. Because it runs Ubuntu 26.04 LTS and Bianbu OS natively, it is a practical platform for software porting and light AI inference at the edge.
StarFive JH-B100: RISC-V Server BMC
Server manageability is as important as raw compute. The JH-B100 is described as the world's first RISC-V architecture baseboard management controller (BMC) / server management chip. A BMC provides out-of-band power control, remote console, thermal monitoring, and firmware update capabilities independent of the host CPU. Having a RISC-V BMC means a RISC-V server can be managed with a RISC-V chip rather than an Arm or 8051-based controller.
| Attribute | Value / Feature |
|---|---|
| Function | Server BMC / management processor |
| ISA | RISC-V |
| Significance | First RISC-V architecture BMC chip |
| Interfaces | IPMI/Redfish-style management, remote console, power/thermal control |
| Benefit | End-to-end RISC-V server platform, no foreign-architecture BMC |
Three Chips, One Rack
The combination of LX500, K3, and JH-B100 covers the three layers a rack needs:
| Layer | Chip | Role |
|---|---|---|
| Compute / AI | BlueChip LX500 | 48-core RISC-V + 75 TOPS NPU, DDR5 + CXL 2.0 |
| Edge / reference | SpacemiT K3 | First RVA23 mass-production chip, compact server boards |
| Management | StarFive JH-B100 | RISC-V BMC for out-of-band control |
This is the first time a RISC-V server can be assembled from RISC-V parts at every level: host CPU, AI acceleration, and platform management. That matters for supply-chain resilience and for security reviews that prefer a single ISA across the board.
Ecosystem Context: Dishui Lake Forum and RISC-V Summit China
The 5th Dishui Lake China RISC-V Industry Forum on August 13, 2026 showcased ten new RISC-V chips spanning AI servers, edge AI, robotics, automotive electronics, and wireless connectivity. The LX500, K3, and JH-B100 were among the headline parts. Forum data showed over 40 RISC-V chips promoted across five editions, with a reported 90% mass-production rate and several chips shipping in the millions.
On September 10, 2026, RISC-V International announced the RISC-V Summit China 2026 in Shenzhen, October 18–20. The event is positioned as one of the largest RISC-V ecosystem gatherings of the year and will likely include production server hardware based on the parts discussed here.
Software and Firmware Readiness
Hardware is only half the story. The server platform spec needs firmware (OpenSBI, U-Boot, EDK2), an OS, and management agents. The current state:
- Ubuntu 26.04 LTS ships with native RVA23 support and runs on K3 hardware today.
- Canonical is moving riscv64 baseline to RVA23 from Ubuntu 25.10, with ~95% package parity vs amd64.
- OpenSBI / U-Boot already support the hypervisor, IOMMU, and PCIe requirements in the Server Platform Spec.
- LLVM / GCC support the RVA23 extension set, including vector and bit-manipulation intrinsics.
Roadmap and Open Questions
RISC-V in the server is real, but still early. The open questions for the next 12–18 months are:
- Benchmarks at scale: Production MySQL, Redis, and web-server benchmarks on LX500-class hardware against x86 and Arm equivalents.
- Binary portability: Will RVA23 be enough to let one Linux distribution image run across LX500, K3, and future server chips without per-board patches?
- Developer tooling: Profiling, debug, and telemetry tools are still behind the x86/Arm ecosystems.
- Supply chain: Long-term availability and second sourcing for server-grade RISC-V SoCs.
Conclusion
2026 is the year RISC-V server silicon stopped being a conference demo and started showing up in production racks. The LX500 provides a credible CPU+AI socket, the K3 validates the RVA23 software baseline in real hardware, and the JH-B100 closes the management loop. With the Server Platform Spec 1.0 ratified and Ubuntu 26.04 LTS native, the foundation is in place. The next milestone is sustained volume deployment by hyperscalers and enterprise OEMs.