SiFive Performance P570 Gen 3: Data-Center-Grade RISC-V IP
SiFive's third-generation Performance P570 raises the bar for high-performance RISC-V processor cores with the most modern RVA23 ISA profile support, out-of-order execution, and data-center-targeted features.
The $400M Bet on RISC-V Data Centers
In August 2026, SiFive closed an oversubscribed $400 million Series G financing round led by Atreides Management, valuing the company at $3.65 billion. The stated goal: accelerate high-performance RISC-V CPU and AI IP solutions into the heart of the data center and AI infrastructure markets. The flagship product driving this vision is the SiFive Performance P570 Gen 3 — the most powerful and efficient out-of-order RISC-V processor core in its class.
P570 Gen 3 at a Glance
| Architecture | RVA23-compliant 64-bit RISC-V |
| Execution | Out-of-order superscalar |
| ISA Extensions | RV64GC + V (Vector) + Zkn (Crypto) + H (Hypervisor) + Zba/Zbb/Zbs |
| Microarchitecture | 3rd-generation Performance series |
| Target Markets | Data center, AI inference, automotive, high-performance embedded |
| Process Nodes | Optimized for 3nm, 5nm, and 7nm |
| Cache Config | Configurable L1/L2/L3 hierarchy |
| Virtualization | Full RVH hypervisor support with nested virtualization |
| Security | Scalar crypto, memory tagging, trusted execution |
What Makes Gen 3 Different
SiFive's third-generation Performance cores represent a significant leap over the P500 series. Key architectural improvements include:
- RVA23 Profile Support: The P570 is the first SiFive core fully optimized for the RVA23 application profile, ensuring binary compatibility across the RISC-V server ecosystem.
- Enhanced Branch Prediction: Improved predictor accuracy reduces pipeline flushes, directly boosting IPC (instructions per clock) across data-center workloads.
- Wider Execution Engine: Increased dispatch and retire bandwidth sustains higher throughput for memory-intensive and vector-heavy code.
- Advanced Vector Unit: Full RVV 1.0 support with expanded VLEN configurations for AI and HPC workloads.
- Coherent Multi-Core: Native support for coherent multi-cluster configurations up to 64+ cores via CHI interconnect.
Data Center Feature Set
Unlike earlier RISC-V cores targeting embedded or mobile, the P570 Gen 3 is explicitly designed for server-class deployment:
- PCIe Gen5 / CXL 3.0: Native high-speed I/O for accelerators, NVMe, and memory expansion
- DDR5 / HBM3 Memory: Supports the latest memory standards with ECC and memory tagging
- Advanced Interrupt Architecture (AIA): Scalable interrupt delivery for many-core systems
- IOMMU and DMA Remapping: Critical for virtualization and device security in multi-tenant environments
- RAS (Reliability, Availability, Serviceability): Error correction, poison data handling, and diagnostic features matching ARM/x86 server standards
Performance Positioning
SiFive positions the P570 Gen 3 competitively against ARM Neoverse N2 and Intel Xeon E-cores. While exact SPECint numbers are under NDA, public statements indicate the P570 delivers:
- Per-core performance in the same class as ARM Cortex-A78 / Neoverse N1
- Significantly higher performance-per-watt than previous SiFive generations
- Vector throughput competitive with ARM SVE implementations for AI inference
Software Ecosystem
A processor is only as good as its software stack. SiFive has invested heavily in toolchain and OS support:
- GNU toolchain: Fully upstreamed GCC, Binutils, and GDB support
- LLVM/Clang: Optimized code generation with P570-specific scheduling
- Linux: Mainline kernel support for RVA23, IOMMU, PCIe, and interrupt controllers
- Hypervisors: KVM and Xen ports validated on P570 RTL models
- Containers: Docker and Kubernetes tested on P570-based reference platforms
Use Cases and Target Designs
The P570 Gen 3 is expected to appear in several classes of products:
- AI Inference Servers: Paired with SiFive's Intelligence X390 NPU or external GPUs for edge-to-cloud AI
- Storage Controllers: High-throughput NVMe-oF and CXL memory pooling controllers
- SmartNICs / DPUs: Offloading networking, security, and virtualization from host CPUs
- Automotive SoCs: ASIL-B/D capable variants for autonomous driving compute
Comparison with SpacemiT X100
| Feature | SiFive P570 Gen 3 | SpacemiT X100 |
|---|---|---|
| Vendor | SiFive (USA) | SpacemiT (China) |
| Availability | IP licensing (RTL) | Silicon (K1/K3 SoCs) |
| ISA Profile | RVA23 | RVA23 |
| Execution | Out-of-order | Out-of-order (4-issue) |
| Target | Data center / AI / Auto | Edge AI / Robotics / PC |
| Form Factor | Soft IP, customizable | Hard silicon, shipping now |
Industry Impact
The P570 Gen 3, combined with SiFive's $400M war chest, signals that RISC-V is no longer just an embedded play. With RVA23 compliance, server-grade RAS, and competitive performance-per-watt, SiFive is making a credible bid for the data center market — the most lucrative segment of the processor industry.
As RISC-V International CEO Andrea Gallo noted at Summit Europe 2026: "2026 is the year of RVA silicon." The P570 Gen 3 is a key part of that silicon story.