XiangShan + Ruyi: China's Open RISC-V Processor System and Native OS

Overview

At the 2026 Zhongguancun Forum (ZGC Forum) RISC-V Ecosystem Technology Forum, the Chinese Academy of Sciences (CAS) announced two landmark open-source deliverables: the XiangShan open-source high-performance RISC-V processor system and the Ruyi native RISC-V operating system. Together they form what Chinese media calls the country's two "RISC-V open-source root communities" — one for high-performance processor IP and one for systems software.

XiangShan is currently the only open-source high-performance RISC-V processor system with cores, on-chip interconnect IP and development tools fully open-sourced. Ruyi is the first domestic operating system natively designed around RISC-V's new high-performance standards, particularly RVA23. The pairing is intended to solve the classic fragmentation problem where hardware and software teams optimized in isolation.

XiangShan Open-Source Processor System

The XiangShan project is led by the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences and the Beijing Open Source Chip Institute (BOSC). It provides not only processor cores but also the world's first open-source on-chip network (NoC) IPs for data-center and terminal SoCs.

XiangShan Core Roadmap

Generation	Year	Milestone
Yanqi Lake (雁栖湖)	2022	First generation; booted Linux; established the open-source core baseline
Nanhu (南湖)	2024	~Cortex-A76 class; 14nm, 2GHz, 10 SPEC CPU2006/GHz
Kunming Lake (昆明湖)	2025/2026	16.8 SPEC CPU2006/GHz; product-grade delivery
Next-gen	2026+	Joint R&D with Alibaba DAMO Academy XuanTie team; XSAI "general+AI" extensions

Kunming Lake Key Metrics

Architecture	64-bit RISC-V, RVA23 profile
Performance	16.8 SPEC CPU2006 / GHz (measured)
Commercial silicon	SpacemiT V100 server chip: 16.5 SPEC CPU2006 / GHz, 2U server form factor
NoC IP — data center	Wenyu River (温榆河): global first open-source data-center NoC
NoC IP — terminal	Pearl River (珠江): first open-source terminal NoC IP
Repository	GitHub (4000+ stars, 550+ forks)

Why Open-Source High-Performance Cores Matter

Until recently, high-performance processor IP was dominated by a few commercial vendors. XiangShan breaks that monopoly by giving chip makers access to a fully open, Linux-bootable, benchmark-verified core. Because the RTL, microarchitecture and tooling are open, companies can customize the core for AI, networking, storage or embedded applications without paying per-unit royalties for the base ISA implementation.

Ruyi Native RISC-V Operating System

Ruyi is developed by the Institute of Software of the Chinese Academy of Sciences. It is described as the first domestic operating system natively built for RISC-V's latest standards and features, with RVA23 support at its core.

What "Native" Means for RISC-V

• RVA23-first: The OS is designed around the RVA23 application-processor profile rather than back-ported from an ARM/x86 codebase.
• Unified kernel foundation: The "RISC-V Kernel Homology" program launched in February 2025 means openEuler, OpenAnolis and openKylin all share the same RVA23 kernel base, eliminating duplicated per-chip adaptation work.
• Built-in RuyiSDK: A unified development kit for RISC-V toolchains, emulators and documentation.
• Hardware-software co-design: Ruyi is optimized specifically for XiangShan cores, allowing the OS to exploit microarchitectural features rather than treating the CPU as a generic target.

Ruyi Components

openRuyi	The open-source RISC-V native base-software community
RuyiSDK	Integrated toolchain, emulator and documentation SDK for RISC-V developers
RuyiAI	RISC-V-native AI software stack (evolved from BuddyCompiler work)
Supported distros	openEuler RVA23, OpenAnolis RVA23, openKylin RVA23
Standards	Native RVA23 support

Getting Started with XiangShan

The XiangShan RTL and simulation environment are hosted on GitHub. Below is a minimal workflow to clone the repository and run the pre-built simulation.

# Clone the XiangShan repository
git clone https://github.com/OpenXiangShan/XiangShan.git
cd XiangShan

# Initialize submodules (Chisel, rocket-chip, etc.)
git submodule update --init --recursive

# Build the simulator (requires Java/Scala/SBT and Verilator)
make emu CONFIG=MinimalConfig -j$(nproc)

# Run Linux on the simulator
./build/emu -b 0 -e 0 -i ./ready-to-run/linux.bin

For detailed build instructions, refer to the OpenXiangShan GitHub repository.

RuyiSDK Quick Start

RuyiSDK provides a one-stop environment for RISC-V development. It can manage toolchains, QEMU and board support packages.

# Install RuyiSDK package manager
wget https://github.com/ruyisdk/ruyi/releases/latest/download/ruyi-installer.py
python3 ruyi-installer.py

# List available toolchains and packages
ruyi list

# Install a RISC-V GCC toolchain
ruyi install gnu-plct

# Activate the toolchain
ruyi venv -t gnu-plct myenv
source ./myenv/bin/ruyi-activate

More details are available at the RuyiSDK GitHub repository.

Commercial Impact

Several companies have already productized chips based on XiangShan:

• SpacemiT V100: Server chip based on Kunming Lake, delivered in 2U server form factor, fully RVA23 compliant.
• XinDong Technology, Lanxin Computing and others: Developing XiangShan-based SoCs for data-center and AI applications.
• RedRISC (开芯红): The exclusive industrialization platform of BOSC, recently raised a 100M+ RMB seed round to commercialize XiangShan CPU, NoC and AI Core IP.

Official Resources

• OpenXiangShan GitHub Repository
• RuyiSDK GitHub Repository
• Beijing Open Source Chip Institute (BOSC)
• CAS XiangShan + Ruyi Announcement (Chinese)
• RedRISC Seed Round Announcement