The Big Picture: A Third Server-CPU Option
For two decades, the datacenter CPU conversation has been binary: Intel x86 or AMD x86 on one side, Arm on the other. At Hot Chips 2026, NVIDIA used its tutorial slot to make a clear claim: RISC-V is on track to become a genuine third server-CPU option for its GPU platforms, sitting beside x86 and Arm.
This was not a vague vision. NVIDIA's presentation listed the exact specifications a RISC-V processor must meet to run CUDA workloads and to plug into the NVLink Fusion fabric that stitches together the company's newest AI factory racks. The company also said it expects a viable third server-CPU option in roughly two silicon generations.
NVIDIA already uses RISC-V for lower-level controllers in its platforms. The Hot Chips 2026 presentation was about host CPUs — the main processor that runs the OS, CUDA driver stack, and application code alongside NVIDIA GPUs. This is a fundamentally different and much bigger commitment.
CUDA Sets the First Compatibility Target
NVIDIA's CUDA platform divides work between the host CPU and the GPU. The CPU handles control flow and sequential code while the GPU runs parallel kernels. A RISC-V host must support the application itself, CUDA libraries, drivers, development tools, and third-party software.
NVIDIA wants developers to run the same application binary across RISC-V processors without rewriting code for each chip. That requires a defined baseline across processors with different implementations.
The RISC-V Baseline: RVA23, Boot Services, and ACPI
NVIDIA points to two specifications as the floor for any RISC-V server silicon:
- RVA23 Profile — guarantees a set of mandatory ISA extensions so that code compiled for one RISC-V core runs on another without falling back to a lowest common denominator.
- RISC-V Boot and Runtime Services specification (ratified August 2025) — defines how firmware hands off to an OS.
- ACPI 6.6 (UEFI Forum ratified May 2025) — provides hardware discovery and power management.
Together, these specs give the hardware a predictable software surface — something the RISC-V ecosystem has historically lacked.
PCIe Coherence and Peer-to-Peer: Non-Negotiable
CUDA data movement follows a strict path: host-to-device copy, kernel launch, device-to-host copy, and CPU work in between. NVIDIA insists on two hard requirements:
- PCIe I/O Coherence — hardware keeps CPU and device views of memory aligned, which reduces cache flush and invalidate operations. Without it, constant software-managed flushes would cripple performance.
- PCIe Peer-to-Peer (P2P) — a GPU can write straight into another GPU's device memory and signal the host with a flag, eliminating an extra hop through system memory. This capability was the reason GPU servers adopted exotic topologies a decade ago.
Vera Rubin NVL72: The Target Architecture
The Vera Rubin platform is a co-designed AI factory spanning seven chips and five racks. The flagship NVL72 rack packs 72 GPUs into a single copper L1 domain. Each compute tray holds:
- GPUs on NVLink Fusion chiplets
- Two Vera CPUs
- Chip-to-chip (C2C) links between CPU and GPU
A custom RISC-V CPU would sit on that same C2C fabric, sharing a unified memory space with the GPUs through CHI coherence.
NVLink Fusion: Adding a Second Layer of Requirements
A CPU that plugs into NVLink Fusion inherits every CUDA requirement and then adds more. The platform contract includes:
| Requirement | Specification |
|---|---|
| ISA Profile | RVA23 (mandatory extensions for binary compatibility) |
| Firmware | RISC-V Boot & Runtime Services (ratified Aug 2025) |
| Hardware Discovery | ACPI 6.6 (ratified May 2025) |
| PCIe Coherence | Hardware I/O coherence (no software flush overhead) |
| PCIe P2P | Direct GPU-to-GPU memory writes with host signaling |
| C2C Interconnect | ~88 PCIe lanes of bandwidth with CHI coherence |
| Networking Stack | DOCA (NVIDIA networking offload framework) |
| Multi-GPU Comms | NCCL (NVIDIA Collective Communications Library) |
| OS Support | Linux (Ubuntu 26.04 LTS, RHEL 10) |
Server builders now have a published checklist. Evaluate a RISC-V SoC against it the same way you would evaluate an x86 or Arm part. Verify RVA23 support, firmware compliance, and OS compatibility before comparing CPU performance. Test PCIe coherency, peer-to-peer transfers, and NVLink C2C behavior. A CPU with strong general-purpose benchmarks could still limit a GPU server if it adds overhead to memory transfers.
SiFive Named as First RISC-V NVLink Fusion Partner
NVIDIA's slides call out SiFive as the NVLink Fusion CPU partner that uses the RISC-V ISA. This is a significant signal — SiFive has been the most visible commercial RISC-V core vendor, and its inclusion suggests NVIDIA is ready to qualify a real silicon implementation rather than a paper design.
This relationship places RISC-V in the host-CPU discussion, beyond the lower-level controllers that already use the architecture in some NVIDIA platforms. SiFive's BigSky SF-2U870 development server (announced at Hot Chips 2026) already runs CUDA on its P870-D cores, demonstrating the path is real.
Timeline: Two Generations Out
NVIDIA's own roadmap language says the company is maybe two generations from broader RISC-V processor deployment in its platforms. That timeline lines up with the typical silicon development cycle:
- Spec finalization (RVA23, Boot/Runtime Services, ACPI 6.6 — done)
- Tape-out (next 12–18 months)
- Qualification and volume production (thereafter)
The open-standard argument — multiple vendors, room for customization — is the same one that helped Arm gain a foothold in the data center a decade ago. The difference is that RISC-V's royalty-free model could lower the barrier even further.
Ecosystem Context
NVIDIA's announcement does not exist in isolation. Several parallel developments make the RISC-V server story credible in 2026:
- SiFive BigSky SF-2U870 — 32 P870-D cores at 2.0 GHz, RVA23-compliant, with Ubuntu 26.04 LTS and RHEL 10 out of the box. CUDA already running. First rackable 2U RISC-V server.
- RVA23 Server Platform Specification 1.0 — ratified by RISC-V International, defining the common ISA baseline for server-class silicon.
- Quintauris RT-Europa — Bosch, Infineon, NXP, Qualcomm, Nordic, ST's joint venture released the first automotive RISC-V platform spec, open for licensing since January 2026.
- SHD Group forecast — RISC-V projected to capture 33.7% of all hardware segments by 2031.
What Builders Should Measure
NVIDIA gave no benchmark results or power figures for a RISC-V host CPU, leaving those tests for future silicon. Builders should record:
- Wall power during host-only work, GPU data transfers, and sustained multi-GPU workloads
- Transfer latency for host-to-device and device-to-host copies under PCIe coherence
- P2P throughput between GPUs with the RISC-V host in the path
- C2C link behavior if the CPU is on the NVLink Fusion fabric
Vendors will need to publish idle, transfer, and full-load measurements before customers can compare platforms against x86 and Arm baselines.
For current builds, x86 and Arm remain the practical choices for NVIDIA GPU hosts. But NVIDIA's Hot Chips 2026 presentation puts RISC-V on a credible path toward becoming a third server-CPU option. The architecture can broaden vendor choice, while NVLink Fusion gives custom CPU designers a route into NVIDIA's GPU ecosystem. Wider deployment will depend on processors that deliver the required compatibility, transfer behavior, and power efficiency in real systems.