From $0.1 MCU
to 60 TOPS AI SoC

Automotive-Grade RISC-V: Infineon’s AURIX RC1 and the Qualification Stack Behind It

On 4 November Infineon put its flagship automotive MCU line on RISC-V: AURIX RC1 scales to 12 32-bit cores, an edge-AI parallel unit, 40 MB of embedded memory and a planned 64-bit MCU/MPU tier, targets ASIL D, and ships with post-quantum-ready security plus the DRIVECORE software stack — samples in H1 2027. Our analysis sets the release against China’s CCDC CCRC4XXX, which is already sampling with a TÜV-certified compiler stack, and finds the one datum neither vendor published: the ISA string. Without it, no tier-1 can judge whether a certified build covers the core.

Infineon Moves AURIX onto RISC-V: RC1 Scales to 12 Cores, 40 MB and ASIL D, Sampling in H1 2027

Announced in Munich on 4 November, AURIX™ RC1 is “Infineon’s first MCU platform that leverages the benefits of RISC-V” — and it is not a side line: RC1 merges AURIX and TRAVEO™ T2G into one basis spanning zone, body and chassis control, BMS, powertrain, ADAS safety management and cockpit. The family integrates up to 12 32-bit cores, one edge-AI parallel processing unit and up to 40 MB embedded memory, with a planned lineup adding 64-bit microprocessor capability. Safety targets ASIL D; security cites ISO/SAE 21434, the EU Cyber Resilience Act, crypto-agility and post-quantum readiness; networking covers CAN-XL, 10BASE-T1S and multi-Gigabit Ethernet with BRIGHTLANE™ switching on selected devices. Concept at electronica (10–13 Nov); samples targeted H1 2027. No ISA string, clock, process node or benchmark was disclosed.

China Mobile Opens an RISC-V Datacenter Validation Base; LX500 Measures 200% Over the Previous RISC-V Generation

China Mobile Research Institute has built and opened a shared RISC-V datacenter test base — one server with ECC memory, NVMe and high-speed networking, running a RISC-V OS, database and web middleware — with a dual-track method that fixes SPEC CPU 2006/2017, sysbench, schbench, openssl (RSA-2048, AES-128-CBC), lmbench and STREAM parameters while also running a real backup workload. The first validated machine was Lanxin LX500, reported at 200% the overall performance of the previous RISC-V generation; a backup management system was ported end-to-end with China Mobile Zhejiang. More consequential for the ISA: CMRI has taken 5G/6G physical-layer complex-number arithmetic — MIMO equalisation, precoding, channel estimation — into RISC-V International as a vertical extension over the matrix extensions, with the complex multiply-accumulate architecture definition complete and a draft spec plus toolchain simulation in hand. Operator-reported figures, no absolute scores published.

XuanTie C950 Takes the “China Chip” Grand Innovation Award as RISC-V Crosses 70 Points on SPECint2006

At the 21st “China Chip” awards in Hengqin on 2 November, Alibaba DAMO Academy’s XuanTie C950 server-class RISC-V processor IP won the Annual Major Innovation Breakthrough Product award — the selection’s top category. The 3.2 GHz core pairs an 8-wide decoder and 16-stage pipeline with a >1,000-entry out-of-order window, and is credited with the first RISC-V SPECint2006 single-core score above 70 (>22 per GHz). New platform details from the event: full RVA23.1 standard and optional extension coverage, native CoVE confidential computing, and Vector + Matrix engines sharing a unified address space with the core — enabling native inference of Qwen3.8-Flash-Next, Qwen3.5-4B, Qwen3-235B-A22B and DeepSeek V4-Flash on the CPU itself. First C950-based server systems are expected next year. Vendor-reported figures.

“China Chip” RISC-V Ecosystem Demo Cases: SpacemiT K3 Joins Zijing’s M100 Automotive MCU

The 21st “China Chip” selection also named its RISC-V ecosystem demonstration cases on 2 November. SpacemiT’s K3 — the first RVA23-compliant RISC-V chip in volume production — took the award two years after the K1 became the first RISC-V high-performance compute chip to win a “China Chip” award in 2024; the citation credits upstreaming work with the open-source community on Linux and base-software enablement. Hunan-based Zijing Semiconductor’s M100, an automotive-grade RISC-V MCU built to in-house reliability standards (high safety, strong real-time, low power), was named alongside it; the company ships its own toolchain and debug environment and is running joint validation with Tier-1 suppliers. Both are ecosystem awards, not product certifications.

SpacemiT K3 Named Among the Ten “Treasures of the Hall” at Wuzhen Internet of Light Expo

When the 2026 “Internet of Light” expo opened in Wuzhen on 2 November (671 exhibitors from 54 countries), the editorial team of Communications Industry Report picked ten “treasures of the hall” — and the only chip among them is SpacemiT’s RISC-V AI CPU, the K3. The selection cites its homogeneous fusion architecture of 8× X100 cores (up to 2.4 GHz) plus 8× A100 1024-bit RVV AI cores, 130 KDMIPS general compute and 60 TOPS AI at a 15–25 W window, LPDDR5-6400 up to 32 GB, and smooth local execution of 30B-parameter models. It is described as the first RVA23-compliant RISC-V chip in volume production, already deployed in Beijing and Shanghai humanoid-robot innovation centres. Specs match SpacemiT’s official K3 brief.

XuanTie-Licensed RISC-V Chip Shipments Pass 6 Billion Cores Across ~400 Licensees

Reporting on Alibaba DAMO chief scientist Jianyi Meng’s Shenzhen summit disclosure, Chinese tech media put XuanTie-licensed cumulative shipments above 6 billion chips — up from ~2.5 billion in mid-2023 and 4 billion in March 2024 — across ~400 licensed companies and 1,000+ licenses (figures as reported by the vendor). The growth base remains embedded control: power metering, Wi-Fi, PMICs, AI glasses. Upmarket, the E908A (first RISC-V CPU IP with both ASIL-B and ASIL-D, SPFM >90%) is entering vehicles, while C950 (3.2 GHz, SPECint2006 >70 single-core) partners ramp BMC, networking and GPU/storage-controller parts, with first XuanTie-950-based servers expected next year.