1. Overview
On September 9, 2026, Suzhou Ruixin Integrated Circuit Technology Co., Ltd. announced that its self-developed High-Beam D35 (Gao Guang D35) dataflow AI chip has entered mass production. It is positioned as the world's first RISC-V dataflow architecture physical AI chip, combining three key innovations:
- Full dataflow architecture — no program counter, no instruction scheduling; data readiness triggers computation automatically, delivering higher compute-unit utilization, lower data movement, deterministic latency, and superior energy efficiency
- Self-developed high-performance RISC-V CPU core — recognized by Intel as the only globally approved procurement, demonstrating RISC-V's advancement into high-end computing
- 128 GB large-capacity memory — supports large-scale AI model deployment at the edge with high-throughput video encode/decode capabilities several times that of comparable edge GPUs
ISCA 2026 Best Paper Nominee: The dataflow computing research behind High-Beam D35 was nominated for best paper at ISCA 2026, the most prestigious and longest-running academic conference in computer architecture. This represents the international top level for Chinese teams in this field.
2. Dataflow Architecture: From MIT to Mass Production
The dataflow architecture concept was first proposed by MIT Professor Jack Dennis in the 1960s. Unlike traditional control-flow architectures, dataflow uses a "data-driven computation" model where data readiness automatically triggers computation, eliminating the need for program counters and instruction scheduling.
Control Flow vs. Dataflow: An Analogy
Control flow is like a cafeteria line: someone directs traffic, everyone queues up, steps forward one at a time, and gets served when called. Dataflow is like a buffet: all dishes are laid out, you take what you want, and when one dish runs low it's naturally replenished — no one needs to direct traffic.
Four Key Advantages of Dataflow
| Advantage | Explanation | Impact on AI Inference |
|---|---|---|
| Higher compute-unit utilization | No instruction-scheduling overhead; compute units stay busy | GPU utilization often <30% in edge inference; dataflow eliminates this bottleneck |
| Less data movement | Data flows directly between compute units; no repeated memory read/write | Reduces memory bandwidth pressure and energy waste |
| Deterministic latency | No branch prediction failures, no cache misses | Critical for real-time control in robotics and autonomous systems |
| Higher energy efficiency | Control-flow overhead eliminated; more work per watt | Physical AI scenarios are power-constrained; efficiency gains are the key metric |
These characteristics make dataflow architecture inherently suited for AI inference — especially physical AI, where edge-side power, size, and cost constraints are hard limits.
3. High-Beam D35 Key Specifications
| Parameter | Value |
|---|---|
| Chip name | High-Beam D35 (Gao Guang D35) |
| Architecture | Full dataflow (data-driven, no program counter) |
| ISA | RISC-V (64-bit) |
| CPU core | Ruixin self-developed high-performance RISC-V core (Intel globally recognized) |
| Memory | 128 GB large-capacity on-board memory |
| Video encode/decode | Several times throughput of comparable edge GPUs |
| Target deployment | Edge-side and terminal-side physical AI acceleration |
| Academic recognition | ISCA 2026 best paper nominee |
| Status | Mass production (announced 2026-09-09) |
Why 128 GB matters: Large memory allows bigger AI models to run locally at the edge — data stays on-device (security), no network round-trip (speed), and works offline (reliability). These three dimensions combined unlock use cases that cloud-dependent architectures cannot serve.
4. Self-Developed RISC-V CPU Core & Intel Recognition
The High-Beam D35 integrates a high-performance RISC-V CPU core fully self-designed by Ruixin. This core received Intel's sole global procurement recognition, validating that RISC-V is no longer synonymous with "low-end embedded" and is advancing into high-end computing territory.
This recognition carries significance beyond the chip itself. It demonstrates that the open RISC-V ISA can produce CPU cores that meet the procurement standards of the world's largest semiconductor company — a powerful signal for the entire RISC-V ecosystem.
The timing aligns with RISC-V's commercial inflection point in 2026: Ubuntu 26.04 LTS became the first enterprise OS with native RISC-V optimization, the RISC-V Server Platform Specification 1.0 was ratified, and SHD Group forecasts RISC-V reaching 33.7% total market share across all hardware segments by 2031.
5. Four Physical AI Application Scenarios
Based on the dataflow architecture's technical characteristics, High-Beam D35 targets four physical AI application domains:
| Scenario | Description | Why Dataflow Fits |
|---|---|---|
| Industrial Intelligence | AIPC acceleration, video compression & analysis, industrial smart control | High compute utilization + video codec throughput handles more channels per unit cost |
| Embodied AI | Robots, autonomous vehicle domain controllers — perception + decision + control integration | Low latency, high energy efficiency, and deterministic timing match hard real-time constraints |
| Cockpit-Driving Integration | Smart cockpit + driving-domain perception on a single chip | Large memory + mixed workload processing enables concurrent AI apps and driving compute |
| Communications | 5G small cells, mmWave, AI RAN | Architecture advantages in power, size, and reliability align with telecom-grade requirements |
6. Glorious Community: Ecosystem Strategy
Hardware performance ultimately depends on software ecosystem maturity. Ruixin launched "Glorious Community" (Guang Rong She Qu) alongside the chip — the world's first RISC-V dataflow developer community.
The community is not a simple forum but a complete resource platform integrating:
- Documentation center
- SDK toolchain
- Model library
- Online training
- Technical support
Ruixin also established the Ruixin Glorious Fund to support ecosystem innovation, providing a global testing ground for RISC-V and dataflow developers.
7. Industry Context: Global Dataflow Investment Wave
Global tech giants have been aggressively investing in dataflow technology, validating its strategic value for the inference era:
| Company | Action | Significance |
|---|---|---|
| NVIDIA | $20B acquisition of Groq dataflow technology license + core team absorption | Largest dataflow IP deal in history |
| AMD | Acquired Canadian dataflow inference chip company Taalas | Expands AI inference portfolio beyond GPU |
| Intel | Dataflow investment and in-house development | Strategic hedge on post-GPU architecture |
| Samsung | Dataflow investment and in-house development | Diversification beyond Arm-based custom silicon |
| Ruixin | High-Beam D35 mass production (RISC-V + dataflow + physical AI) | First to combine all three paradigms in a shipping chip |
8. About Ruixin
Suzhou Ruixin Integrated Circuit Technology Co., Ltd. is headquartered at No. 90 Yun Hui Road, Suzhou Industrial Park. Founded in August 2020, the company focuses on RISC-V CPU + dataflow LPU (Language Processing Unit) AI chip design, aiming to provide an efficient, autonomous, and open computing foundation for the physical AI era.
- Chief Scientist: Sun Ninghui, academician of the Chinese Academy of Engineering and national strategic scientist
- Core Team: Veterans from IBM, Intel, and top research institutions
- Academic output: 100+ published papers, dozens of patents
- Focus: RISC-V CPU + dataflow LPU AI chips for physical AI