StarFive Dubhe-100: First Deliverable Server-Grade RISC-V HPC CPU IP
On August 18, 2026, StarFive announced Dubhe-100 (昉·天枢-100), the first deliverable server-grade RISC-V CPU IP core, with 15/GHz SPECint2006 matching Arm Cortex-A78. This deep dive covers its 15-stage deep out-of-order pipeline, RVA23 compliance, vector unit, scalability to 256 cores per die, and what it means for RISC-V's data-center roadmap.
Overview
On August 18, 2026, StarFive (赛昉科技) officially launched Dubhe-100 (昉·天枢-100) — a high-performance, server-grade RISC-V CPU IP core targeting HPC and AI agent workloads. It is the first domestically deliverable server-class RISC-V CPU IP, and the first licensee (LECARC / 希奥端计算) has already selected it for smart edge-server CPUs. Linux, KVM, and both Type-1 and Type-2 hypervisors run on the platform.
The headline numbers are:
- 15 / GHz integer IPC (SPECint2006) — matching Arm Cortex-A78
- 15-stage deeply out-of-order pipeline
- 6-issue width superscalar
- 256-entry out-of-order instruction window (ROB)
- Industry-leading out-of-order vector execution unit
- Full RVA23 profile compliance
- Scalable from 1 to 256 cores per die (single/dual/quad cluster configs)
- Industry-standard interconnect: TileLink, AXI, ACE, CHI
Key Specifications
| Vendor | StarFive (赛昉科技) |
| Product Name | Dubhe-100 (昉·天枢-100) |
| Announced | August 18, 2026 |
| Target Market | Server / HPC / AI-Agent / Smart Edge |
| Architecture | RV64GCV + RVA23 profile extensions |
| Pipeline | 15-stage, deeply out-of-order |
| Issue Width | 6-wide superscalar |
| Reorder Buffer | 256 entries |
| Integer IPC | 15 / GHz (SPECint2006) |
| Performance Parity | Arm Cortex-A78 (single-thread) |
| Vector Unit | RVV with OoO execution |
| Virtualization | Type 1 + Type 2 hypervisor (validated) |
| Cluster Configs | 1 / 2 / 4 cores per cluster |
| Maximum Cores per Die | 256 (via TileLink mesh + StarNoC-700 NoC) |
| Interconnect | TileLink, AXI, ACE, CHI |
| Linux Support | Validated, KVM operational |
| RVA23 Compliance | Yes (vector, hypervisor, crypto, bit-manip all included) |
| First Licensee | LECARC (希奥端计算) — smart edge server CPUs |
Architecture Deep Dive
15-Stage Deep Out-of-Order Pipeline
The 15-stage pipeline is one of the deepest among RISC-V server-class cores. Compared to a typical in-order 5-7 stage design (such as WCH's QingKe V4F), or a moderate 8-10 stage OoO design (such as SiFive's P270), Dubhe-100 pushes the pipeline depth substantially further. This trade-off buys higher clock frequencies at the cost of branch misprediction latency.
For an HPC design that is less branch-intensive than database or JVM workloads, a deep pipeline is a good fit. The deeper pipeline also enables more aggressive speculation and out-of-order dispatch — both required for the high IPC.
6-Issue Width Superscalar
Six operations can be dispatched, issued, and executed per cycle. Combined with the 256-entry reorder buffer, the core can keep many execution units busy simultaneously. Typical RISC-V application cores stop at 2-issue (WCH QingKe) or 3-issue (SiFive P550). 6-issue puts Dubhe-100 in the same league as Cortex-A77 / A78 / A710.
256-Entry Out-of-Order Window
The ROB is the heart of an OoO design. A 256-entry window allows the core to look across 256 instructions for parallelism. This is enough to hide the latency of off-chip L3 cache accesses, page-table walks, and most integer-multiply/divide operations.
For context: the original SiFive P550 had a ~80-entry window. SiFive's P870 Gen 2 raised this to 192 entries. StarFive Dubhe-100 lands at 256, matching what one would expect from a contemporary ARM Neoverse N2-class core.
Out-of-Order Vector Execution Unit
Most RISC-V cores implement the vector unit (RVV) in program order. StarFive claims an out-of-order vector unit — a meaningful departure from the conservative baseline. This allows vector instructions to be re-ordered to avoid long-latency vector memory waits, important for AI inference kernels with sparse activation patterns.
Industry-Leading RVA23 Compliance
Dubhe-100 implements the complete RVA23 application profile mandated by RISC-V International:
- RV64GC base (IMAFDC)
- V vector extension (with StarFive's OoO vector unit)
- H hypervisor
- Zkn / Zks scalar crypto
- Zba / Zbb / Zbs bit manipulation
- Zicbom / Zicboz / Zicbop cache-management ops
This means Dubhe-100 will run Ubuntu 26.04 LTS, Debian RISC-V, OpenAnolis, and Bianbu Linux unmodified, alongside standard GNU toolchains upstream.
Multi-Core Scalability
Cluster Configuration
Dubhe-100 supports three cluster topologies out of the box:
- 1-core cluster (most area-efficient)
- 2-core cluster (typical SMT-disabled mode)
- 4-core cluster (L2 shared coherent)
NoC Integration and 256-Core Scaling
Multiple clusters are stitched together using StarFive's own StarNoC-700 (昉·星路-700) network-on-chip IP. Customers can build:
- 4-core → 16-core → 64-core mesh topologies
- Up to 256 cores in a single die via TileLink/CHI coherent mesh
- Larger NUMA domains for server SKUs beyond 256 cores via ACEManaged Coherent Interconnect
This makes Dubhe-100 viable for both edge (4-16 cores) and rack-scale server (32-256 cores) use cases — the same IP, different topology.
Software Ecosystem
Linux
The mainline Linux kernel (6.x LTS branch) supports Dubhe-100. StarFive has upstreamed the core's CPU binding and SBI support.
KVM and Hypervisors
Both Type 1 (bare-metal) and Type 2 (hosted) hypervisors run validated. This unlocks cloud-native virtualization:
- QEMU/KVM accelerated emulation
- Firecracker / Cloud Hypervisor micro-VMs
- Standard OpenStack and Kubernetes deployments
Toolchain
Standard GNU and LLVM toolchains with RISC-V backend produce binaries. Performance-critical code can use StarFive's optimized intrinsic libraries (where released) or standard -march=rv64gcvh / -mabi=lp64d toolchain flags.
First Application: LECARC Smart Edge Servers
LECARC (希奥端计算) has announced it will use Dubhe-100 as the CPU base for its smart edge-server product line. Key use cases for LECARC include:
- On-premise AI inference servers for retail and manufacturing
- Private-cloud edge nodes for telco MEC (Multi-access Edge Computing)
- Sovereign cloud compute servers for government / regulated industries
- AI-agent infrastructure for retrieval-augmented generation (RAG) pipelines
This is significant because it represents a real, named customer for a RISC-V server CPU IP — a milestone the wider ecosystem has been waiting for.
Comparison With Other RISC-V Server CPU IP
| Parameter | StarFive Dubhe-100 | SiFive P870 Gen 2 | Andes AX65 | SpacemiT X100 |
|---|---|---|---|---|
| Year | 2026 | 2025 | 2025 | 2026 |
| SPECint2006 / GHz | 15 | ~14-15 (estimated) | ~12 | 9.41 (single-core) |
| Pipeline | 15-stage OoO | 13-stage OoO | 10-stage OoO | 11-stage OoO |
| Issue Width | 6 | 4 | 3 | 4 |
| ROB | 256 | 192 | 128 | ~128 |
| Vector Unit | RVV OoO | RVV in-order | RVV in-order | RVV 1024-bit (in-order) |
| Hypervisor | Type 1 + 2 | Type 1 + 2 | Type 1 | Full chip |
| Max Cores / Die | 256 (via StarNoC-700) | 128 (mesh) | 64 (mesh) | 8 (cluster) |
| RVA23 | Full | Full | Partial | Full |
| First Customer | LECARC (Aug 2026) | Multiple (shipping) | Announced | K3 SoC (Apr 2026) |
Dubhe-100 lands at the top of the RISC-V server IP performance envelope as of August 2026. Its closest domestic peer is SpacemiT X100 (used in the K3 SoC), but X100 is a chip-ready IP rather than a licensable building block — Dubhe-100 is the first domestically licensable core aimed at third-party server SoCs.
Why This Matters for RISC-V
RISC-V Server Market Moved From Slide to Silicon
For years, the RISC-V server story has been "soon." With Dubhe-100, the timeline is concrete: silicon at this performance level can be designed, validated, and productized within 12-18 months for SoC customers. LECARC's selection removes the "no real customer yet" caveat.
Domestic Licensable IP Reduces External Dependency
For Chinese SoC companies that want server-class RISC-V silicon without licensing from a US-headquartered vendor (SiFive is US-based), Dubhe-100 provides an alternative. This matters for both geopolitical risk and supply-chain diversification.
Cortex-A78 Parity Is Real, Not Marketing
15 SPECint/GHz is the published number, and matches A78 within the typical ±5% methodology variance. Combined with RVA23 compliance, this means a Dubhe-100 cluster can effectively replace an A78 cluster in most server workloads.
Limitations and Open Questions
A few items that are not yet public:
- Frequency target at typical process (does StarFive target 2.5 GHz? 3.0 GHz?)
- Power envelope for a single core at 100% load
- Whether the core is licensable directly or only via StarFive's SoC partnership program
- List of confirmed customers beyond LECARC
- Benchmarks under real workloads (database, JVM, AI inference)
These will likely emerge in subsequent announcements over Q4 2026 / Q1 2027.