Overview
At Hot Chips 2026 (August 25, Santa Clara), XCENA — the South Korean computational-memory startup formerly known as MetisX — and Samsung Electronics jointly presented the MX1 computational-memory device. The chip integrates 3,072 in-order RISC-V cores alongside up to 2 TB of DDR5 on a single expansion card manufactured on Samsung's 4 nm process. The pitch is simple: memory has not gotten smarter while CPUs and GPUs have. MX1 makes memory a programmable compute tier that can run selected jobs where the data sits.
XCENA's thesis: instead of moving data to the processor, bring the processor to the data. For bandwidth-bound workloads (vector search, KV-cache, memory compression, analytics kernels), processing on-card eliminates transfers over the CXL link and reduces host CPU load.
Hardware Architecture
| Parameter | Specification |
|---|---|
| Process Node | Samsung 4 nm |
| Compute Cores | 3,072 in-order RISC-V cores @ 1.1 GHz |
| Core Clustering | 32 cores → 1 cluster; 4 clusters → 1 subsystem (128 cores); 24 subsystems per chip |
| Management Cores | 2× Arm Cortex-A53 |
| Host Interface | PCIe 6 + CXL 3.2 x8 (128 GB/s aggregate) |
| Downstream PCIe | 8 lanes (for SSD connectivity) |
| Memory | Up to 2 TB DDR5 (as DIMM on card) |
| SSD Tier | "Infinite Memory" — SSD exposed as byte-addressable memory; DDR5 acts as cache |
| Compute Power | ~40 W (compute chip); ~90 W (board with 4 DIMMs) |
| AI Throughput | ~3 TFLOPS dot-product (vector engines) |
| Parallelism | 24 independent subsystems — each can accept a separate job |
Core Hierarchy
The 3,072-core count is structured in a clean hierarchy that allows independent job dispatch:
- 32 cores form one cluster
- 4 clusters (128 cores) form one subsystem
- 24 subsystems on the chip, each accepting separate jobs
Two Arm Cortex-A53 cores manage the device, handle scheduling, and interface with the host. The RISC-V cores themselves are in-order designs — they are not general-purpose replacements for server CPUs. Their purpose is narrow: run bandwidth-bound kernels where data locality matters more than single-thread performance.
Memory Subsystem: DDR5 + "Infinite Memory"
The card carries up to 2 TB of DDR5 DIMMs. But the真正的 innovation is the SSD tier, which XCENA calls "Infinite Memory":
- Attached SSDs are exposed to the host as byte-addressable memory — not as block storage
- The card's DDR5 serves as a faster cache in front of the SSD tier
- Caching and prefetching attempt to hide SSD latency
- This provides considerably more capacity than DRAM alone could offer
The utility of this design depends on whether the caching layer can hide enough SSD latency for a given workload. For sequential access patterns and large working sets that exceed DRAM capacity, the benefit is clear. For latency-sensitive random access, the DDR5 cache must hit at a high rate.
Host Interface: PCIe 6 + CXL 3.2
MX1 connects to its host over a PCIe 6 and CXL 3.2 x8 interface, providing 128 GB/s of aggregate host bandwidth. This is significant because:
- CXL 3.2 allows the card to participate in coherent shared memory with the host
- Host applications and MX1 can operate on the same virtual addresses, reducing pointer translation and data copying
- Eight downstream PCIe lanes connect SSDs directly to the card, bypassing the host entirely for data ingestion
Software Stack
Hardware alone is not enough. XCENA's software layer is where the bet lives or dies:
| Component | Description |
|---|---|
| Language Support | C/C++ and Rust |
| Drivers | Host-side drivers for CXL device discovery and management |
| Simulation Tools | Pre-silicon simulation for software development before hardware availability |
| Runtime | "Parallel Xceleration Library" — a MapReduce-style runtime for dispatching jobs across the 24 subsystems |
| Memory Model | Shared virtual address space between host and MX1 — no data copies needed |
Hyperscalers are unlikely to rewrite mature inference and data-processing systems solely to adopt a memory card. XCENA needs the MX1 offload path to fit into existing frameworks (PyTorch, vLLM, etc.) and produce savings large enough to justify another programmable device in the server.
Rack-Scale Reference Design
Samsung used the Hot Chips platform to show MX1 beyond a single add-in card. According to ServeTheHome's coverage of the slides, Samsung and XCENA presented a reference design connecting GPU servers and MX1 devices through a CXL switch:
- Shared memory pool: 20 TB capacity
- Aggregate bandwidth: 2.7 TB/s
- GPU servers access the pooled memory through the CXL fabric
- MX1 devices process selected workloads in-memory, reducing GPU idle time on data movement
Samsung and XCENA reported results from two selected AI workloads, but no independent reproductions have been published.
Target Workloads
The 3,072 cores provide roughly 3 TFLOPS of dot-product throughput — modest compared to a modern GPU, but the point is not raw FLOPS. MX1 targets workloads where data movement, not compute, is the bottleneck:
- Vector search — similarity scoring on large embedding datasets stored in DDR5/SSD
- KV-cache handling — LLM inference cache management with near-data processing
- Memory compression — in-line data compression to extend effective memory capacity
- Analytics kernels — columnar scans, aggregations, and filtering on data that exceeds DRAM
Company Background
XCENA was founded in early 2022 under the name MetisX by Jin Kim (former SK hynix VP, next-gen architecture), CTO Dohun Kim, and CPO Harry Juhyun Kim. The three founders came from Samsung and SK hynix, with backgrounds spanning memory architecture, SoC design, and software. The company rebranded from MetisX to XCENA in late 2024.
XCENA is based in Pangyo (Seongnam, South Korea) with an office in Sunnyvale, California. As of May 2026, the company employed more than 90 people across both locations. The Hot Chips presentation followed the company's $135 million Series B in May 2026. Production target: late 2026.
What This Means for RISC-V
MX1 is a notable data point for the RISC-V ecosystem for several reasons:
- Scale of deployment: 3,072 RISC-V cores per card represents one of the largest single-device RISC-V core counts in a commercial product
- Domain-specific architecture: The cores are in-order and narrow-purpose, validating RISC-V's use in domain-specific accelerators rather than just general-purpose CPUs
- Open ISA in memory: Using RISC-V for computational memory shows the ISA's flexibility in unconventional compute architectures
- Foundry partnership: Samsung 4nm manufacturing signals foundry-level confidence in RISC-V-based designs at advanced nodes