CH32H417 Dual-Core RT-Thread: Official Porting Example and Dual-Core Debug Notes

The CH32H417 is WCH's flagship ultra-high-speed MCU: two QingKe RISC-V cores (a RISC-V5F application core paired with a V3F assist core), 5 Gbps USB 3.0, an integrated 100M Ethernet PHY, dual high-speed ADCs and DACs, PDUSB, and UHSIF support. It is exactly the kind of part where "which RTOS do I run?" becomes a real question - and this week the WCH community gave a clear answer.

What the Thread Established

A developer asked the question many have been quietly asking: has anyone successfully ported RT-Thread to the CH32H417, and how do you actually synchronize and debug across the two cores?

WCH staff (TECH62) replied with two concrete resources:

An official RT-Thread example for CH32H417, distributed by email on request from the WCH support team
A dual-core debugging application note, published as thread 144462 on the WCH BBS, which walks through cross-core debug methodology

The thread drew 13 replies, nearly all of them engineers requesting the example package for their own evaluation - a strong demand signal that RT-Thread on this dual-core part is on many 2026 shortlists.

Why Dual-Core Debug Is the Hard Part

Porting an RTOS to a single core is routine. The CH32H417's difficulty is coordination:

Boot split: firmware must bring up each core with its own vector table and stack before the scheduler starts
Cross-core communication: shared-memory mailboxes or hardware-mediated signaling between the 5F and V3F cores
Debug visibility: you need to halt, inspect, and single-step each core without wedging the other - which is precisely what the WCH dual-core debug application note covers, including how to attach the debugger to a non-boot core

The practical recipe from the thread:

1. Request the official CH32H417 RT-Thread example from WCH support 2. Study the dual-core debug application note (wch.cn/bbs/thread-144462-1.html) 3. Verify basic inter-core signaling with a bare-metal test before enabling the RTOS on both cores 4. Debug each core from a separate MounRiver Studio session as described in the app note

Where This Fits in the WCH RISC-V Ladder

If you are sizing up the family: the CH32V307 ($3) remains the workhorse single-core part with Gigabit Ethernet MAC, the CH32V317 ($4) adds 480 Mbps USB to that profile, and the CH32H417 ($6) is the step up to USB 3.0 plus dual-core compute. The same MounRiver Studio toolchain covers all of them, so an RT-Thread investment on a V307 carries forward to the H417.

Source: CH32H417移植rtthread - WCH BBS thread 159661 and the WCH dual-core debug application note thread 144462. Condensed and translated from the public WCH community discussion.