Weekly highlights compiled by AI from community discussions
A two-track hands-on guide from the SpacemiT community: run x86 Steam games on K3 via felix86 emulation with an AMD RX550 GPU, and build open-source retro FPS engines natively on RISC-V.
Two recent Chinese community deep dives cover WCH's motor-focused RISC-V lineup: the CH32M006A8U7 that integrates a full-bridge power stage into a 3x3 mm QFN16, and the CH32V007/M007 pairing for BLDC square-wave and FOC control up to 24 V systems.
A community developer built the Flutter engine for riscv64 Linux from source on a SpacemiT K3, ported the LocalSend desktop GUI, and fixed a Skia fontconfig bottleneck that slows first frame on every GTK4/Chromium app under Bianbu.
Three open-source hardware projects from OSHWhub worth building: a CH32V003F4P6 core-board backplane for learning peripherals, a programmable fingerprint dock keyboard on CH32V203 with shift-register key scanning, and a WCH-LinkW wireless debugger based on CH32V208.
At RISC-V Summit China 2026, SpacemiT launched the V100 server CPU combining six Xiangshan Kunminghu V2R2 cores with 40 of its own X100 cores, plus three server platforms. It is claimed to be the first processor fully compliant with the RISC-V server specifications.
A look at four recent WCH RISC-V MCU discussions from the Chinese community: the low-power USB-PD CH32L103, the BLE+dual-USB CH583, the 48 V motor-control CH32M007, and Ethernet tips for the CH32V307.
A SpacemiT K3 developer reports that the Linux-6.18 signal-handling path trusts user-controlled vstate.vlenb without validation when CONFIG_SPACEMIT_HMP=y, pointing to a specific line in arch/riscv/kernel/signal.c.
The forum was quiet this week, so as promised we published an honest RISC-V vs ARM comparison for product planners - covering where ARM still wins, where RISC-V wins on cost and freedom, a realistic hybrid K1-gateway + WCH-MCU architecture, and a practical 2026 decision framework.
A community member hit intermittent GRUB/HDMI display failures on Milkv Jupiter 2 with Bianbu-LXQt-UEFI-K3 v4.0.7 while building a Bianbu+Gentoo multiboot - a practical checklist for anyone dual-booting K3 boards.
A meticulous community bug report pins SpaceMITExecutionProvider numerical errors on K3 to the attention Q.KT MatMul in EmbeddingGemma-2, with a full tensor-dump localization methodology - plus why you should validate EP output against CPU EP today.
The forum was quiet this week, so following last week's preview we published a complete hands-on setup guide for WCH MounRiver Studio - the free Eclipse-based RISC-V IDE - covering installation, first project creation, LED blink, WCH-LinkE flashing, debugging, and scaling from the $0.1 CH32V003 up to Gigabit Ethernet and USB 3.0 parts.
The forum was quiet this week, so following last week's preview we published a complete hands-on setup guide for WCH MounRiver Studio - the free Eclipse-based RISC-V IDE - covering installation, first project creation, LED blink, WCH-LinkE flashing, debugging, and scaling from the $0.1 CH32V003 up to Gigabit Ethernet and USB 3.0 parts.
Run the CH32V307 EVT Ethernet demo unmodified on a CH32V317 and the link stays down. WCH staff confirm the fix: swap the driver file to eth_driver_CH32V317.c, which brings up the chip's internal 100M PHY.
Fresh-from-factory CH32V005 chips stay silent on the PD0/PD1 UART bootloader. WCH confirms factory-blank parts have no IAP installed, and points to the SDI-first workflow or WCH-LinkE as the reliable routes.
A WCH forum user caught a real documentation bug: the reference manual's PWM Mode 1 edge-aligned section inverts the output polarity compared with the OCxM register description. WCH confirmed the manual text is wrong and the register description is authoritative. Here is the corrected rule.
WCH has confirmed an official RT-Thread porting example for the CH32H417 dual-core RISC-V MCU, together with an application note covering dual-core debugging. Thirteen replies of engineers requesting the package show how strong the demand is - here is what the thread establishes and how to get started.
K3 OpenBLAS wide-core optimization, a confirmed architecture bug in mepc handling, CH32H417 USB endpoint independence, and CH32V307 memory config pitfalls — plus a complete K1 OpenWrt compile-and-flash tutorial.
WCH confirms CH32V307 FLASH and RAM sizes are configurable via LinkUtility, but mismatched ld script settings cause mysterious firmware failures. Here's how to keep them in sync.
WCH officially confirms that CH32H417's USB 3.0 SS and USB 2.0 HS controllers are fully independent peripherals, allowing simultaneous use of the same endpoint numbers on both interfaces.
A detailed analysis of a K3 bug where mepc loses bit63 during instruction page faults on non-canonical addresses under Sv39, violating RISC-V Privileged Architecture requirements.
OpenSolvers ported OpenBLAS to K3's wide A100 cores (VLEN=1024) and ran HPL. The result: stock ZVL256B kernels run 3.5x slower on A100 than X100, but custom ZVL1024B tiles recover 2.4x. Mixed 8+8 ranks hit 57.5 GFLOP/s.
The forum was quiet this week, so we published a complete hands-on tutorial instead: compiling OpenWrt 23.05 from source for the SpacemiT K1 and flashing it to SD card and eMMC, covering build-host setup, menuconfig, fastboot partition maps, and first-boot verification.
A community post from Sep 19 shows MounRiver Studio II, WCH's official RISC-V IDE, working with a DeepSeek harness attached - another sign that LLM-assisted development is moving into vendor toolchains, and a practical look at what that means for CH32-class MCU work.
WCH's official forum confirmed on Sep 20 that the CH32H417 can run lwIP, though no official example ships yet. Here is what the in-house WCHNET stack gives you today, and the practical path to bring lwIP up on the H417's RGMII-based Ethernet.
A practical walkthrough of machine-mode interrupt and exception handling on WCH CH32V RISC-V MCUs: the CSR pipeline (mtvec, mcause, mepc, mstatus), the attribute declarations the WCH toolchain expects, and five classic pitfalls when coming from ARM.
The CH32V002 upgrades the CH32V003 family with a QingKe RISC-V2C core and RV32EmC ISA, adding hardware integer multiply and divide instructions for motor control and DSP-style loops.
A custom CH32H417 board froze when running USBHS Wi-Fi with tickless SysTick; switching to a fixed 1 ms SysTick resolved the symptom, pointing to a SDRAM timing/interaction issue.
A community porting note explains how the CH32V307 V3A core handles interrupt nesting, why FreeRTOS critical sections need care, and the one-line assembly fix to enable nested interrupts.
A common CH579 issue: pulling the Ethernet cable is not always reflected in the link state. WCH support explains how to use PHY_Change interrupt plus WCHNET_GetPHYStatus() and provides an updated driver library.
A reproducible HardFault on CH32V307 when I2S2 RX DMA1_Channel4 and the WCHNET Ethernet library are both used. The developer's isolation tests point to a DMA1 vs Ethernet MAC interaction.
A K3 Pico-ITX user found that installing kdump-tools triggers update-grub, which regenerates GRUB entries without the required device tree blob. Here is the workaround and the upstream fix preview.
This week the forum was quiet, so we bring you a hands-on guide to configuring mwan3 multi-WAN load balancing on OpenWrt 23.05 with SpacemiT K1, covering policy design, traffic steering, and failover testing on dual-RGMII architectures.
A 21ic community benchmark shows how RISC-V vector extension hand-tuning can deliver a 5.3x speedup for a 512-point radix-2 FFT on the XuanTie C906.
A practical guide to RISC-V startup code, linker script memory layout, and common boot-time pitfalls translated from the 21ic community.
A community experiment testing the high bits of the mhpmevent3 register on SpacemiT K3 reveals which RISC-V privilege-level inhibition fields are actually implemented.
A deep-dive into the Zig Software Foundation's report of stale/incorrect code execution on SpacemiT K3 when paired with the WD Black SN7100 NVMe SSD, including symptoms, workarounds, and current status.
A case study of a CH32H417 custom board where CAN frames could be transmitted but not received, and the systematic steps that isolated the root cause.
Practical lessons from building USB HID devices on WCH CH32V series RISC-V microcontrollers, covering transceiver wiring, descriptor alignment, and debug tooling.
A step-by-step guide to toggling an LED on the WCH CH32L103 RISC-V MCU by directly manipulating clock, GPIO configuration, and output registers.
Researchers propose a self-evolving LLM-agent workflow that learns hardware-specific optimization experience from initial solutions, targeting emerging platforms like SpacemiT K1 and K3.
W36 had a quiet week on the forum threads aggregator, so this digest focuses on a single deep-dive: running a 7B-parameter quantized LLM locally on the SpacemiT K3 with llama.cpp, plus the WCH MCU roadmap for Q4 2026.
A practical Q&A on where to store the MAC address during SpacemiT K3 production: dedicated EEPROM, flash, or UFS partition.
A low-cost open-source USB Type-C power meter built around the WCH CH32V003 RISC-V MCU and TI INA219. Covers hardware design, PD passthrough caveats, DCDC power supply, and firmware approach.
An overview of the WCH CH32H417 dual-core RISC-V MCU: QingKe V5F + V3F big.LITTLE-style cores, boot order, development workflow, and where it fits in high-performance connected embedded designs.
A practical guide to calling the 2x2x4[x2] MAC unit on SpacemiT K1 through the RISC-V IME extension and vmadot instruction, with build and run instructions.
A real-world case where a CH32V307 ADC pin measured 3.7V due to 5V back-feeding from an RS485 transceiver. Covers root cause, diagnosis steps, and design guidelines for mixed-voltage MCU systems.
A practical guide to binding PCIe NVMe SSDs to vfio-pci on the K3 CoM260 for SPDK, covering the default IOMMU-disabled path with NOIOMMU mode and enabling IOMMU via device tree.
SpacemiT's August 2026 upstream report covers Triton backend merging into FlagTree, llama.cpp Qwen3-ASR support, major Linux kernel K1/K3 patches, and 30+ box64 RISC-V fixes.
本周论坛暂无新帖，为大家带来 CH32V003 入门教程：从 LED 闪烁到 USB 设备与 2.4G RF，快速上手 WCH 沁恒 RISC-V MCU。
Community member chenjiayi published a complete Live2D desktop pet implementation on Bianbu Desktop (LXQT) running on SpacemiT K1 and K3. Built with Cubism Web and GTK3, this is the first usable Live2D pet on RISC-V desktops.
A developer community member successfully executed real LLM decoding on Orange Pi RV2 (SpacemiT K1 X60) using ONNX Runtime's int4 MatMulNBits path, MLAS CompInt8, and smt.vmadot instructions. This article summarizes the technique and its implications.
WCH's CH398 combines a 5 Gbps USB 3.0 PHY with a full Gigabit Ethernet MAC+PHY in a single chip, offering a compact and cost-effective USB-to-Ethernet adapter solution compatible with mainstream operating systems.
A community developer has requested SpacemiT to release the source code of its modified OpenOCD required for K3 JTAG debugging, citing GPLv2 obligations. This highlights the broader importance of open-source compliance in the RISC-V ecosystem.
The OpenSolvers team achieved real LLM decode on the SpacemiT K1 (X60) using ONNX Runtime's MatMulNBits with IME smt.vmadot instructions, reaching ~80 ms/token for Qwen2.5-0.5B int4 -- a 200x improvement over the default compute path.
A community-consolidated answer to one of the most common CH32V newcomer questions: which WCH RISC-V MCUs have an FPU, and how to tell from a project setting alone. Short version: only the V300, V400 and H417 families currently have single-precision FPU, and the official QingKe core manual is the authoritative source.
SpacemiT (Bianbu) has announced a proactive recall of K3 CoM 260 Kit 8GB units shipped between August 4 and 14, 2026 due to a probabilistic PCB failure risk caused by a substrate material change. Other batches and 4GB / 16GB variants are not affected.
A practical JTAG debugging setup for the SpacemiT K3 CoM260 board using only commercial, off-the-shelf parts: a SparkFun MicroSD breakout board and an FT2232H Mini Module. No custom PCB needed.
本周论坛共 2 个活跃话题，编辑精选 2 篇精华，覆盖 CH32V407 Hits 3.10 CoreMark/MHz (17% Over CH32V307): Why RVV Vector Extension Changes the Game, Migrating STM32 to CH32V307: RISC-V Low-Level Differences for FreeRTOS / RT-Thread 等方向。
本周论坛共 2 个活跃话题，编辑精选 2 篇精华，覆盖 CH32V407 Hits 3.10 CoreMark/MHz (17% Over CH32V307): Why RVV Vector Extension Changes the Game, Migrating STM32 to CH32V307: RISC-V Low-Level Differences for FreeRTOS / RT-Thread 等方向。
A working GFXBench 5.1.5 build on SpacemiT K3 + Bianbu (riscv64) closes a major gap in cross-platform GPU benchmarking on RISC-V. Build recipe, caveats, and ecosystem context.
In LLVM 23 / Binutils 2.47, the SpacemiT X60 schedule model has become the default -mtune=generic reference for RISC-V. A look at what shipped in July 2026 and why it matters.
A working GFXBench 5.1.5 build on SpacemiT K3 + Bianbu (riscv64) closes a major gap in cross-platform GPU benchmarking on RISC-V. Build recipe, caveats, and ecosystem context.
In LLVM 23 / Binutils 2.47, the SpacemiT X60 schedule model has become the default -mtune=generic reference for RISC-V. A look at what shipped in July 2026 and why it matters.
本周论坛共 1 个活跃话题，编辑精选 1 篇精华，覆盖 LinkW: Open Source Wireless Programmer Based on CH32V208 等方向。
Step-by-step guide to building RenderDoc on Bianbu Linux riscv64, including Qt5 to Qt6 migration, deployment, and frame capture on PowerVR BXM-4-64.
A community QEMU fork supports CH32V003/V103/V203/V303/V305/V307/V317/V407 and CH32H417, enabling firmware validation, network emulation, and CI/CD without hardware.
本周论坛共 2 个活跃话题，编辑精选 2 篇精华，覆盖 CH32V317 Flash Clock Frequency Configuration Guide, How to configure mwan3 load balancing on K1 with dual WAN? 等方向。
本周论坛共 2 个活跃话题，编辑精选 2 篇精华，覆盖 CH32V317 Flash Clock Frequency Configuration Guide, How to configure mwan3 load balancing on K1 with dual WAN? 等方向。
An open-source hardware testing platform brings CI/CD automation and AI agent integration to the $0.10 CH32V003 RISC-V MCU, with GitHub Actions, self-hosted runners, and remote development capabilities.
A new source-based Linux distribution built on CRUX brings the KISS philosophy to the SpacemiT K1 platform, with dual kernel options and 1.8GHz overclocking support.
Step-by-step guide for switching K1 MUSE Pi Pro display output from MIPI-DSI to HDMI, including DTS configuration and troubleshooting black screen issues.
Community contributor adds SpacemiT K1 processor support to RustSBI firmware project, including important UART clock rate fix for Orange Pi RV2.
This week: mwan3 load balancing on K1, RISC-V networking tips, and K1-8G product spotlight.