CH32H417 USB 3.0 and USB 2.0 HS Endpoint Independence: Official WCH Clarification

A common question when working with the CH32H417 — WCH's flagship dual-core RISC-V MCU with USB 3.0 (5 Gbps) — is whether the USB 3.0 SuperSpeed (SS) and USB 2.0 High-Speed (HS) endpoints conflict. A developer recently asked on the WCH forum:

> "CH32H417 has USB 3.0 SS and USB 2.0 HS in the same physical USB interface. If I configure USBSS endpoint 1IN and 1OUT, can I still use USBHS endpoint 1IN and 1OUT?"

WCH's official answer is clear and unambiguous:

> "The USB 3.0 SS controller and USB 2.0 HS controller are independent, belonging to two independent peripherals. Configuring USBSS endpoint 1IN and 1OUT does not affect USBHS — you can still use USBHS endpoint 1IN and 1OUT. The USB 2.0 interface in a USB 3.0 port exists for backward compatibility."

What This Means for Developers

The CH32H417 packs two complete USB controllers behind one Type-C connector:

Feature	USB 3.0 SS	USB 2.0 HS
Speed	5 Gbps	480 Mbps
Endpoint numbering	Independent	Independent
Simultaneous operation	Yes	Yes
Purpose	High-bandwidth data	Backward compatibility / debug

This independence has practical benefits:

Dual-protocol devices: You can build a composite device where USB 3.0 handles bulk data transfer (e.g., video, high-speed ADC samples) while USB 2.0 handles HID or CDC for control and debugging — all on the same connector.
Endpoint budget doubled: Since endpoint numbers are per-controller, you effectively have twice the endpoint resources. Endpoint 1 on SS and endpoint 1 on HS are distinct hardware resources.
Graceful fallback: If the host only supports USB 2.0, the HS controller takes over automatically. Your firmware does not need to reconfigure endpoints — the SS controller simply never enumerates.
Firmware architecture: You can develop and test the HS stack first (easier debugging, wider host compatibility), then add the SS stack for production performance without touching the HS code.

CH32H417 at a Glance

Cores: QingKe RISC-V5F + V3F (dual-core)
USB: 5 Gbps USB 3.0 + 480 Mbps USB 2.0 HS, both with independent endpoint controllers
Ethernet: Built-in 100 Mbps PHY
ADC: Dual high-speed ADCs
DAC: Dual DACs
Other: PDUSB, UHSIF support
Price: ~$6

The CH32H417 sits at the intersection of high-speed data and embedded control. Its USB 3.0 + Ethernet PHY combination makes it ideal for data-acquisition front ends, industrial gateways, and high-speed sensor interfaces. The independent endpoint architecture removes a common source of confusion and lets developers treat the two USB interfaces as the separate peripherals they actually are.

Source: CH32H417 USB3.0/USBHS endpoint independence — WCH official forum response Looking for RISC-V MCUs? The WCH CH32H417 ($6, USB 3.0 + Ethernet) and the full CH32V series are available at open-riscv.com.