SpacemiT V100: A 46-Core RISC-V Server CPU Built on Xiangshan Kunminghu Cores

SpacemiT V100: A 46-Core RISC-V Server CPU Built on Xiangshan Kunminghu Cores

On October 19, 2026, at the RISC-V Summit China in Shenzhen, SpacemiT officially launched the V100 server-class CPU and unveiled three matching server platforms covering compute, AI acceleration, and storage. The headline claim: V100 is the industry's first general-purpose processor to fully implement the RISC-V server specification stack, with native support for mainstream server operating systems and virtualization.

This is a milestone beyond the K1 and K3 we cover regularly on Open RISC-V. It marks RISC-V's transition from edge and terminal devices into the data center.

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The Heterogeneous 46-Core Design

V100 was co-developed with the Xiangshan (香山) team and is the first silicon to ship the Xiangshan Kunminghu core in a production processor:

• 6x Xiangshan Kunminghu V2R2 cores - 13-stage, 6-wide out-of-order pipeline, up to 2.1 GHz, 1 MB private L2 each
• 40x SpacemiT X100 cores - 12-stage, 4-wide out-of-order pipeline, up to 2.4 GHz, 2 MB shared L2
• Manufactured on a 12 nm process, 120 W TDP
• Dual-socket cache-coherent interconnect scaling up to 92 cores
• 8x DDR5-4800 memory channels and 52 lanes of PCIe 5.0

Both core types fully support RVA23, virtualization (CPU, interrupt, and I/O virtualization works with upstream Linux KVM - no custom kernel required), PMP/ePMP, and Debug and Trace. Hardware root of trust and server-class RAS features are included.

Full Server Specification Compliance

V100 implements five specifications end to end: RVA23 Profile, RISC-V Server SoC Specification, Server Platform Specification, Boot and Runtime Services (BRS), and the RISC-V Security Model. BRS compliance tests have passed in full, which means UEFI, ACPI, and SMBIOS all work as expected.

The practical consequence: mainstream Linux distributions install and boot directly. Ubuntu 26.10 officially supports V100, and openEuler, openRuyi, openKylin, Debian, Ubuntu, Fedora, Red Hat, and Rocky are all reported to run out of the box. This is the x86-style deployment model - one distro image, many server chips - rather than the per-board kernel tuning that has plagued earlier RISC-V server attempts.

Three Server Platforms

• C2201 - general-purpose compute server
• G5201 - AI/acceleration server, fits eight full-height full-length double-width accelerator cards, validated with Kunlunxin and other vendors, with RDMA networking for clusters
• S5236 - storage server

SpacemiT is supplying server motherboard reference designs, firmware, BMC support, and hardware design documentation so system builders can develop servers under their own brands.

The Xiangshan Milestone

For the open-source hardware community this launch carries extra weight: it is the first time an open-source processor core (Xiangshan Kunminghu, developed under the Institute of Computing Technology of the Chinese Academy of Sciences and the Beijing Open Source Chip Institute) has gone from IP release through product-level co-validation to volume silicon. The lineage: Yanqihu (2021, ~A73 class), Nanhu (2023, ~A76 class, later adopted in GPU chips shipping in volume), Kunminghu (2024, Neoverse N2 class), and now Kunminghu V2R2 in a shipping product.

SpacemiT Product Ladder

Ecosystem Notes

SpacemiT's processor support and toolchain work has been merged upstream into the Linux kernel and LLVM. The company is working with Canonical, the RISE Project, and Scaleway to give open-source developers access to RVA23-compatible hardware, and is contributing K3 compute clusters to shared development infrastructure. International customers have reportedly placed orders for K3 chips and K3-based cluster servers, with DeepComputing and Banana Pi bringing K3-based mainboards, dev boards, and compute modules (including Framework mainboards) to global markets.

What This Means for Open RISC-V Readers

If you are building on the K1 today - for example our favorite K1 OpenWrt gateway builds - the V100 announcement signals where the platform family is heading: the same RVA23/UEFI/ACPI software discipline now extends upward into rack-scale hardware. For homelab and edge-cloud experiments, a K3 or future V100-class box running a stock Ubuntu image is becoming a realistic target rather than a porting project.

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Sources

• Source: China Daily - Xiangshan Kunminghu core tape-outs and ships for the first time
• Source: GlobeNewswire via Manila Times - SpacemiT Launches 46-Core V100 RISC-V Server CPU
• Source: Phoronix - SpacemiT Announces The V100 Server-Class RISC-V Processor
• Source: EET-China - SpacemiT launches V100 server CPU

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Compiled by Open RISC-V AI Assistant For product inquiries, contact contact@open-riscv.com or visit /forum/inquiry