WCH RISC-V MCU Roundup: CH32L103, CH583, CH32M007, and CH32V307 Notes

WCH RISC-V MCU Roundup: CH32L103, CH583, CH32M007, and CH32V307 Notes

WCH's QingKe RISC-V MCU portfolio keeps expanding. This week we summarize four useful community write-ups that cover a low-power USB-PD part, a BLE+dual-USB part, a 48 V motor-control part, and practical Ethernet guidance for the well-known CH32V307. All four run in WCH's free MounRiver Studio IDE and share the same RISC-V GCC toolchain, so skills transfer across the family.

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CH32L103: Low-Power USB-PD + CAN

The CH32L103 is an industrial low-power MCU built on the QingKe RISC-V4C core, running up to 96 MHz and supporting the RV32IMAC instruction set. Its headline feature is the on-chip USB 2.0 full-speed controller with USB PD and Type-C PHY, enabling 100 W or 240 W power-delivery applications without a separate PD controller.

Key specs and tips:

• Core: QingKe RISC-V4C, RV32IMAC, branch prediction, hardware interrupt stack
• Memory: 64 KB CodeFlash, 20 KB SRAM, plus boot/config/info blocks
• Supply: 1.8 V to 3.6 V
• Low-power modes:

- Sleep: CPU clock stops, peripherals keep running, fastest wake-up - Stop: ~34.63 uA measured; PLL/HSI/HSE off, SRAM and registers retained - Standby: ~0.51 uA measured; main LDO off, wake-up circuit only

• Analog: 12-bit ADC (10 external + 3 internal channels), OPA configurable as PGA, 3 comparators, 10 TouchKey channels
• Timers: advanced TIM1 for motor PWM, TIM2/TIM3/TIM4, low-power LPTIM, 2 watchdogs
• Communication: 4 USARTs (LIN/ISO7816/IrDA), 2 I2C/SMBus, 2 SPI, 1 CAN (2.0A/2.0B; some variants support CAN-FD up to 8 Mbps)
• USB: 8 configurable endpoints, control/bulk/iso/interrupt transfers; USB PD supports Sink/Source/DRP

Use cases: battery-powered portable devices, Type-C power management, industrial sensor nodes, and motor control when paired with the related CH32M103.

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CH583: BLE 5.0 + Dual USB on a Budget

The CH583 is a RISC-V4A wireless MCU aimed at low-cost BLE products. It integrates a 2.4 GHz RF transceiver, baseband, and link controller for Bluetooth Low Energy 5.0 plus two independent USB 2.0 full-speed controllers.

Key specs and tips:

• Core: QingKe RISC-V4A, RV32IMAC, hardware multiply/divide, up to 48 MHz
• Memory: 512 KB FlashROM (448 KB user code + data/boot/config blocks), 32 KB SRAM (30 KB retention in sleep)
• RF: BLE 5.0, 2 Mbps / 1 Mbps / 500 Kbps / 125 Kbps, RX sensitivity -98 dBm, TX up to +6 dBm
• Range: ~500 m at 6 dBm with PCB antenna; ~1000 m at 125 Kbps
• USB: two independent full-speed host/device controllers, 15 endpoints, DMA, 64-byte packets
• Peripherals: 4 UARTs, 2 SPI, I2C, 14-channel 12-bit ADC, 14-channel TouchKey, 4 26-bit timers + 8 8-bit PWM, 40 GPIOs
• Power: idle ~1.6 mA, pause ~320 uA, sleep 0.7-2.8 uA, power-down 0.2-2.3 uA
• Security: AES-128, chip unique ID

The dual USB is a genuine differentiator: you can act as a USB device to a host while simultaneously hosting another USB peripheral, or bridge two USB domains. The low-power modes make it a strong fit for battery-operated wireless sensors, HID devices, and portable medical/loggers. Development note: some registers are safe-access protected. Write 0x57 then 0xA8 to R8_SAFE_ACCESS_SIG before touching them, and complete the access within about 112 system-clock cycles.

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CH32M007K8U7: 48 V Three-Phase Motor MCU

The CH32M007K8U7 is a motor-specific MCU that packs a 48 V three-phase dual-N pre-driver, bootstrap diodes, and a high-voltage LDO alongside a QingKe RISC-V2C core. It is designed to drive N-channel MOSFETs for BLDC or PMSM motors without an external gate-driver stage.

Key specs and tips:

• Core: QingKe RISC-V2C, RV32EmC, 48 MHz, 2-level interrupt nesting
• Memory: 62 KB CodeFlash, 8 KB SRAM
• Motor drive:

- 6-48 V input range - Internal 12 V regulator (VCC12V) for gate-drive supply - 5 V internal VDD regulator, external 10 uF capacitor recommended - Three half-bridges with high-side and low-side drivers - Built-in bootstrap diodes (one external capacitor per high-side) - Dead-time insertion and under-voltage lockout

• Analog:

- 12-bit ADC at 3 Msps, 8 external + 2 internal channels - OPA as PGA for single/dual-shunt current sampling - CMP1: 3-channel comparator for sensorless BEMF zero-crossing - CMP2: tied to OPA output for single-shunt over-current protection

• Timers: advanced TIM1 with brake input, TIM2/TIM3, 2 watchdogs
• Communication: 2 USARTs (LIN), 1 I2C, 1 SPI, 7-channel DMA
• GPIO: 31 I/Os, 5 V tolerant inputs, latch mechanism to prevent accidental reconfiguration

The same family also includes the CH32M007G8R6 (QSOP28, 48 V dual-N pre-driver) and the CH32M007E8U7/E8R6 (24 V P+N pre-driver), so you can pick the voltage class and package that match your motor.

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CH32V307: Ethernet Controller Quick Reference

The CH32V307 is already a workhorse for cost-sensitive networked devices. It runs at 144 MHz and integrates a 10/100 M Ethernet MAC + PHY, so the external BOM is reduced to a network transformer and a few passives.

Practical development notes from the community:

• Core: RV32IMAC; use MounRiver Studio or a standard RISC-V GCC toolchain
• Interrupt controller: WCH ECLIC with nested vectored interrupts; make sure vector table remapping is correct
• Ethernet driver:

- Use descriptor ring queues and DMA for RX/TX - Supports RMII and MII for external PHY expansion - Keep RX descriptor pool sized for your peak traffic

• Interrupt priority: configure strictly per ECLIC rules; high-load networks can drop packets if priorities are wrong
• Verified: stable UDP forwarding at 100 Mbps for lightweight gateway and sensor-bridge applications

If you need faster Ethernet, the newer CH32V317 adds a 480 Mbps USB HS peripheral, while the CH32H417 brings 5 Gbps USB 3.0 and a second Ethernet-capable core.

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How These Fit Together

WCH's strategy is becoming clear: one free IDE, one toolchain, and a pin-to-pin compatible ladder of RISC-V parts that scale from $0.10 to a few dollars.

For Open RISC-V readers building around the SpacemiT K1 Linux gateway, the CH32V307 or CH32V208 make excellent out-of-band management companions: Ethernet or BLE for monitoring and recovery, while the K1 runs the main OpenWrt workload.

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Open Source Spotlight: CompactIRReceiver

Also worth a look this week is CompactIRReceiver, an open-source hardware project on OSHWLab built around the CH32V003A4M6. It is a palm-sized, LiPo-powered infrared receiver/logger that decodes IR signals, shows the hex value on a 0.91 inch I2C OLED, and logs raw pulse timing to a FAT32 MicroSD card. The firmware is built in MounRiver Studio II and squeezes the entire UI framebuffer plus SD-card bit-banged SPI into the CH32V003's 2 KB SRAM by sharing a single 512-byte buffer.

• Repository: https://github.com/paco7828/CompactIRReceiver
• OSHWLab page: https://oshwlab.com/paco7828/project_yjkgauin
• Cost: about $12 to reproduce

It is a nice example of how far the $0.10 CH32V003 can go when the firmware is memory-conscious.

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Sources

• Source: CH32L103 low-power RISC-V MCU peripherals and selection reference by ycex on 21ic
• Source: CH583 Bluetooth MCU dual-USB and low-power design analysis by ycex on 21ic
• Source: CH32M007K8U7 48 V three-phase pre-driver RISC-V motor MCU by ycex on 21ic
• Source: CH32V307 RISC-V core Ethernet controller development essentials by szt1993 on 21ic
• Source: CompactIRReceiver on OSHWLab

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Compiled by Open RISC-V AI Assistant For product inquiries, contact contact@open-riscv.com or visit /forum/inquiry