Official Errata: WCH Reference Manual Misstates PWM Mode 1 Edge-Aligned Behavior

Documentation errata confirmed directly by the vendor are gold for anyone writing bare-metal timer code - so when a WCH community member (posting under "bit") challenged the CH32L103 reference manual this week, and WCH confirmed the manual is wrong, it was worth spreading beyond one forum thread.

The Contradiction

The reference manual's edge-aligned PWM overview section states, for PWM mode 1:

> When the core counter value is GREATER than the compare capture register, OCxREF is high; when the counter is less than the compare value, OCxREF is low.

But the OCxM bitfield encoding in the timer register chapter says the opposite:

> 110 - PWM mode 1: while upcounting, the channel is active as long as the core counter is LESS than the compare capture register value, otherwise inactive; while downcounting, the channel is inactive as long as the counter is greater than the compare value.

Both descriptions appear in the same manual, and the poster noted the same contradictory wording repeats across several WCH reference manuals.

WCH Confirms: The Register Description Wins

WCH staff (TECH62) responded within a day, confirming the edge-aligned section is incorrect and that the correct behavior matches the OCxM register encoding:

In PWM mode 1, edge-aligned: OCxREF is HIGH while the core counter value is LESS than the compare capture register value, and LOW when the counter is greater (for example, after the counter wraps from the ATRLR reload value back to zero).

The erratum has been forwarded internally for the manual to be corrected.

Practical Takeaways

Trust the OCxM encoding, not the overview prose: duty cycle in PWM mode 1 equals CCR / ARR with output active during the count-below-compare window
If your waveform polarity looks inverted on a scope, this manual error is the first thing to rule out before suspecting your GPIO remap or complementary-output setup
The same QingKe timer IP family recurs across the CH32V003 ($0.1), CH32V203, CH32V307 ($3), CH32V317 ($4), CH32L103, and CH32M030 lines, so treat this as a family-wide erratum, not a CH32L103-only note
A ten-second logic-analyzer check of one period will confirm polarity on your specific part and firmware

Kudos to the reporter - a polite, precise "these two sections contradict each other" post with quoted text got a same-week vendor confirmation. That is how datasheet quality improves for everyone.

Source: RM文件中PWM模式描述是否是矛盾的 - WCH BBS thread 161653. Condensed and translated from the public WCH community discussion.