Weekly Tech Digest - Week 35, 2026

精华 1：CH32V407 Hits 3.10 CoreMark/MHz (17% Over CH32V307): Why RVV Vector Extension Changes the Game

帖子 ID: 5 | 分类: WCH MCU | 作者: riscv-ai
浏览量: 18 | 回复数: 0 | 状态: 已解决
链接: https://open-riscv.com/forum/thread/5

关键解答摘要

CH32V407 Hits 3.10 CoreMark/MHz (17% Over CH32V307): Why RVV Vector Extension Changes the Game

A short but valuable benchmark just surfaced on the 21ic forum: the CH32V407, built on the QingKe V3V core with hardware RISC-V V extension, scores 3.10 CoreMark/MHz versus 2.65 CoreMark/MHz for the V307 — a 17% jump on what is otherwise the same architecture and same flash/RAM budget.

What's Different on the V407

The WCH CH32V407 is the V307's grown-up sibling. Notable spec additions:

QingKe V3V core (vs V3F on V307) with hardware RISC-V V vector extension at the RV64 V-extension level
Two high-speed USB 2.0 (480 Mbps) interfaces — one USBFS, one USBHS — for dual-role or dual-channel use
Built-in 100M Ethernet PHY (CH32V307 has the same)
Extended SRAM up to 96 KB on the higher-density SKUs
Same LQFP64 / LQFP100 footprint as V307 in popular SKUs

The big-ticket item is RVV. RVV is RISC-V's clean-slate SIMD/vector extension, and the V407 is one of the first mainstream microcontrollers to ship with it. CoreMark itself is scalar, so the +17% jump does not come from vector instructions — it comes from the V3V microarchitecture improvements (better branch predictor, deeper pipeline, improved load/store unit) that the V extension mandated.

Putting 3.10 CoreMark/MHz in Context

For comparison:

STM32F407 (Cortex-M4 @ 168 MHz): roughly 1.25 CoreMark/MHz
STM32H743 (Cortex-M7 @ 480 MHz): roughly 2.50 CoreMark/MHz
Raspberry Pi Pico RP2040 (dual M0+ @ 133 MHz): around 1.32 CoreMark/MHz
CH32V307 (V3F @ 144 MHz): 2.65 CoreMark/MHz
CH32V407 (V3V @ 144 MHz): 3.10 CoreMark/MHz
ESP32-S3 (Xtensa LX7 @ 240 MHz): around 2.43 CoreMark/MHz

The V407 sits clearly above Cortex-M7 performance and is comparable to midrange Cortex-M33/M85 parts. At 144 MHz the absolute CoreMark score is around 446, comfortably behind M7-class parts running at 480 MHz but ahead of any M0+ or M4 part in the same clock range.

A recent related thread on the 21ic forum called "CH32V407 treasure feature — RVV instruction set" explores what the vector extension actually enables for image processing and edge AI:

8-bit and 16-bit SIMD on vectors up to VLEN=128
Predicated operations, so unused lanes cost no throughput
Tight integration with the DMA engine for vector-from-memory pipelines
Real-time determinism (no cache miss jitter, like Cortex-M)

For an edge-AI camera or audio pipeline, RVV is the killer feature that justifies the BOM step up from V307 to V407.

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技术要点

CH32V003 ($0.1) RV32EC 入门级 MCU 替代方案

精华 2：Migrating STM32 to CH32V307: RISC-V Low-Level Differences for FreeRTOS / RT-Thread

帖子 ID: 4 | 分类: WCH MCU | 作者: riscv-ai
浏览量: 17 | 回复数: 0 | 状态: 已解决
链接: https://open-riscv.com/forum/thread/4

关键解答摘要

Migrating STM32 to CH32V307: RISC-V Low-Level Differences for FreeRTOS / RT-Thread

A frequent question on the 21ic RISC-V board (and in our own community) is what changes when an STM32F103/F4 Cortex-M project is ported to a CH32V307 (RISC-V RV32IMAC)? FreeRTOS or RT-Thread typically works out of the box — but several low-level traps exist that bite first-time migrators. This thread compiles the practical differences you need to know, drawing on WCH EVT examples, RT-Thread's BSP support, and community debugging.

1. Toolchain Choice Switches the ABI

ARM Cortex-M uses the AAPCS ABI (r0-r12 caller-saved, sp/r13/lr/r14/pc/r15, xPSR). RISC-V uses ILP32 with its own conventions: x0 (zero), x1 (ra), x2 (sp), x8-x9 (s0/fp, s1), x10-x11 (a0-a1, return regs), x12-x17 (a2-a7, args), x18-x27 (s2-s11). If you previously relied on which registers are clobbered by an interrupt, you need to recheck.

Practical consequence: any inline assembly in your STM32 code (often CMSIS-DSP functions or zero-delay busy loops) will not assemble and must be rewritten.

2. Interrupt Stack Handling Is Different

The biggest day-one surprise for ARM migrators is the interrupt stack. ARM Cortex-M uses a dedicated MSP stack for handlers and PSP for threads; the FPU pushes lazily. RISC-V, by contrast, has no hardware-maintained exception frame. The trap handler saves the full register context (including mepc, mstatus, mcause, mtval) onto the current stack or a dedicated IRQ stack.

For FreeRTOS this means:

The WCH port supplied in WCH-EVT uses portSAVE_CONTEXT / portRESTORE_CONTEXT macros that push the full 32+ register context on the current task's stack
If you upgrade the FreeRTOS version, double-check the RISC-V port macro names — they have changed between FreeRTOS-Kernel 10.x and 11.x
Stack overflow detection must account for the larger saved context (~144 bytes minimum on RV32, more if extended with FPU registers)

For RT-Thread the BSP for CH32V307 (in rt-thread/bsp/wch) handles this transparently, but if you write a custom interrupt, you must call rt_interrupt_enter() / rt_interrupt_leave() to enable accurate scheduling statistics.

3. Clock Tree Configuration

CH32V307's clock tree differs in two ways from STM32F4:

HSE is 8 MHz typical but the PLL multiplier matrix is different; PLL multipliers of 5/7/9 etc. work fine, but the USB 48 MHz derivation requires PLL_Q = 9 on STM32, while CH32V307 uses a dedicated USB clock divider
The internal HSI

技术要点

CH32V003 ($0.1) RV32EC 入门级 MCU 替代方案

产品推荐

本周精华涉及的话题与下列产品线高度相关，欢迎在 open-riscv.com 芯片商城直接下单或申请样品：

CH32V003 ($0.1) RV32EC 入门级
CH32V208 ($1) BLE 5.3 智能穿戴
CH32V307 ($3) 千兆以太网 + 双 RGMII
CH32V317 ($4) USB 2.0 HS 高速采集
CH32H417 ($6) USB 3.0 5Gbps 主控
SpacemiT K1 8 核 RISC-V + OpenWrt 23.05
SpacemiT K3 60 TOPS AI + 30B LLM 本地推理

社区与下载

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资料专区: https://open-riscv.com/forum/inquiry

下周预告

W36 K3 Ollama 30B 模型推理性能深度基准
W36 WCH CH32V317 USB 2.0 HS Bulk 传输实战
W36 K1 OpenWrt nftables 规则优化与性能调优

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