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A 28nm RISC-V Out-of-Order Core Designed by Agents: Inside Cuisi's 6nm Inference Chip Plan

2026-09-16 4 min read EN
RISC-V AI-EDA Agentic-EDA 28nm 6nm Out-of-Order Edge-AI MPW

Table of Contents

Published: 2026-09-16 · Category: RISC-V AI · Reading time: ~4 min · Status: DRAFT

The announcement

On 15 September 2026, Chinese financial outlet STAR Market Daily reported that Shanghai Cuisi Technology (上海淬思科技有限公司, Xuhui District, Shanghai) had closed an angel round of over ¥100 million. The round was led by an undisclosed leading fund, with Yunqi Capital, Monolith Capital and Fudan Sci-Tech participating, following an incubation round closed a few months earlier.

The company was founded in 2026 and develops AI inference chips. Founder Pan Hongyang holds a PhD from Fudan's State Key Laboratory of Integrated Circuits and Systems, works on AI-driven design automation, and won the MLCAD 2025 international competition.

Funding rounds are not normally engineering news. This one is worth reading because of the specific technical claim attached to it.

The 28nm RISC-V out-of-order tape-out is the real signal

The concrete artefact Cuisi points to is an academic tape-out of a 28nm RISC-V out-of-order core that the company says ran the complete flow from specification to layout (GDSII).

That is a meaningful choice of proof point, and worth unpacking. An out-of-order core is not a toy: it carries register renaming, reorder buffers, issue queues, branch prediction and a coherency story, and getting one through the full RTL-to-GDSII chain is a genuine integration test of any design flow. Picking RISC-V as the vehicle is also deliberate — an open ISA means no licensing negotiation, no proprietary ISA compliance gate, and freedom to instrument the flow end to end.

It is also, deliberately, a 28nm part. At 28nm, MPW and full-mask costs are survivable and the physical-design problem is well understood. Using a mature node to prove a design methodology before spending on 6nm is exactly the right sequencing. The node choice is a tell that the company is validating a flow, not chasing a benchmark.

Agentic EDA: what is actually being claimed

Cuisi describes an AI-native chip design flow built on a self-developed Agentic EDA platform that automates the path from design specification to layout. On RISC-V designs, the company says the flow reaches near-zero human intervention, and that it integrates multi-agent scheduling with a closed loop.

Three things that claim does not say, and that a reader should not read into it:

  1. "Near-zero human intervention" is not "no human verification." Whether the produced layout is timing-clean, DRC-clean and functionally correct to a production standard is not addressed in the announcement.
  2. RISC-V-specific is a scope limit, not a general result. Generalising from an open-ISA core to a full inference SoC with analogue and mixed-signal content is unproven.
  3. There is no comparison baseline. No PPA figures, no turnaround-time comparison, no statement of how much human effort was actually required.

The honest framing: this is a claim that agentic methods can carry a real core through a real flow. It is interesting, it is early, and it is unverified.

The 6nm plan: MPW first

The stated next step is a 6nm dedicated inference chip — definition, design and tape-out. The sequencing is explicit and conventional: the first commercial chip maps to a real customer requirement, goes through a 6nm MPW tape-out first, then full-mask tape-out and bring-up.

MPW-first is the standard de-risking move and worth calling out as a positive signal. It caps first-silicon cost, allows multiple design variants on one shuttle, and gets real silicon for characterisation before committing to a full mask set.

First product direction: on-device speech recognition

Cuisi says it is working with several AI-hardware and consumer-electronics customers on model evaluation and joint product definition, with the first direction being on-device speech recognition, and that some customers have formed clear cooperation intent.

On-device ASR is a sensible beachhead. The workload is well bounded, latency-sensitive, privacy-motivated and runs on battery — all properties that favour a dedicated inference part over a cloud round-trip. It is also a crowded segment with strong incumbent MCU-plus-accelerator solutions, so the differentiator will have to be energy per inference, not feature checkboxes.

What is not disclosed

No chip specifications of any kind. Not disclosed: target TOPS, supported precisions, memory configuration, power envelope, die size, package, tape-out date, sampling date, or which foundry. The lead investor is unnamed. The English company name is unconfirmed. No PPA or turnaround data for the agentic flow. No third-party verification of the 28nm result.

None of these has been estimated.

Engineering takeaway

Two threads here are worth tracking separately. First, whether agentic EDA can genuinely shorten the spec-to-GDSII path — if it can, it changes the economics of custom silicon for mid-sized teams, which is a far bigger deal than one chip. Second, whether a 2026-founded team can take a 6nm inference part from MPW to production with a first product in on-device ASR.

Watch for the tape-out announcement, not the next funding round. Silicon, PPA numbers and a named customer are the milestones that will tell you whether either claim holds.

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com