RISC-V Tech Blog

Linux 7.3 RISC-V: Counter Delegation, QoS Tagging and a Busload of New Boards

Linux 7.3 shipped on 2026-10-18 with a large RISC-V pull: Smcdeleg/Smcntrpmf/Sscsrind/Ssccfg counter delegation, Ssqosid QoS tagging context switch, flush-by-ASID plus Svinval in update_mmu_cache_range, and new support for Canaan K230, Milk-V Duo S (SG2000), SpacemiT K3 I2S/SPI/USB and StarFive JHB100.

RISC-V KVM in Linux 7.4: KVM_PRE_FAULT_MEMORY, Four More Guest Extensions, IMSIC Raw Lock

Anup Patel's KVM/riscv 7.4 pull adds KVM_PRE_FAULT_MEMORY, exposes Zicclsm/Ziccamoa/Ziccif/Za64rs to guests, and moves IMSIC wakeup to a raw spinlock.

SpacemiT V100: the First Chip Fully Compliant with the RISC-V Server Specification

At the 2026 RISC-V Summit China in Shenzhen, SpacemiT and the Xiangshan team launched the V100 server CPU: 46 cores (6 Kunminghu V2R2 + 40 X100), 8-channel DDR5-4800, 52 lanes PCIe 5.0, and full compliance with the RISC-V server specification family. Full spec walkthrough.

RISC-V Kernel Auto-Vectorization at LPC 2026: the 15% Headline, and What the Slides Actually Measured

Linux Plumbers Conference 2026 measured an auto-vectorized RISC-V Linux kernel: +15.1% LZ4 compression on one target but -7.5% on K3, and a 0.1% geometric mean across K3 system benchmarks. A close reading of the data.

Ubuntu 26.10 Brings Official RISC-V Desktop Images: SpacemiT K3 Pico-ITX Moves to Supported Hardware

Ubuntu 26.10 adds the first official riscv64 desktop ISO, with SpacemiT K3 Pico-ITX as a supported board. How to install it, run it under QEMU, and what still works.

SpacemiT K1 and K3 Devicetrees for Linux 7.4: CPU Scaling, CTF2301 Fan Control and the CLINT-to-ACLINT Fix

SpacemiT's Linux 7.4 devicetree pull adds K3 CPU scaling, CTF2301 thermal and fan control, USB, rfkill and ACLINT fixes, plus EEPROM MAC for K1 boards.

An SBI Watchdog for RISC-V: Qualcomm Posts a Firmware-Defined Driver With IMSIC Pretimeout

A Qualcomm RFC posted on Oct 2 2026 adds a 406-line RISC-V SBI watchdog driver to Linux: SBI 3.0 gating, a 60 s default timeout, and pretimeout notifications delivered as an IMSIC platform MSI.

gtrace: RISC-V Hardware Trace Heads for Mainline Linux With 14-Patch v6 Series

A v6 14-patch series posted Oct 1 2026 adds gtrace, an architecture-neutral hardware trace framework with the ratified RISC-V E-trace as its first backend: component graph, perf AUX integration, encoder and RAM-sink drivers, plus a QEMU model for testing.

RISC-V IOMMU v6: IMSIC MSI Remapping Turns On IOMMU_DMA and VFIO Device Assignment

Andrew Jones posted v6 of a 16-patch series adding IMSIC MSI remapping to the RISC-V IOMMU driver, enabling IOMMU_DMA and VFIO PCIe device assignment on 64-bit RISC-V — with two documented limitations.

Linux RISC-V TLB Flush Path Tracepoint Reaches v2: Debugging Shootdowns on Real Silicon

Roman 'Hedin' Storozhenko posted v2 of a Linux RISC-V patch that adds riscv_tlb:riscv_tlb_flush_path to observe whether the kernel handles TLB invalidation locally, via SBI RFENCE, or through a cross-CPU call.

KVM on the SpacemiT K3 Reaches Stock Distros: Ubuntu 26.10 Hands-On, a Fedora Com260 Wiki, and Why the BSDs Cannot Boot

KVM works on the SpacemiT K3 under Ubuntu 26.10 mainline 7.3.0 — a Debian 13 guest boots with zvk* vector crypto at 2.37 GB/s AES-GCM. A Fedora wiki covers native KVM on the Com260. All three BSDs fail on rdcycle because the K3 firmware leaves mcounteren.CY and IR clear.

SpacemiT K3 PCIe Root Complex Heads for Upstream Linux: v7 Patch Series

Inochi Amaoto submits v7 of the upstream Linux patch series that adds PCIe Root Complex support for the SpacemiT K3 — a Synopsys DesignWare PCIe controller plus IMSIC, multiple PHYs, and shared K1/K3 driver logic.

Xen Boots on the SpacemiT K3: the First RVA23 RISC-V Board With APLIC, IMSIC and the H-Extension

Xen now boots on the SpacemiT K3 — the only RISC-V board shipping both APLIC/IMSIC and the ratified H-extension. The two-step story from a pre-ratification P550 to a spec-compliant RVA23 board, from the Xen Summit 2026 talk.

Teaching OpenBLAS About the K3's VLEN=1024 AI Cores: HPL on a Heterogeneous RISC-V SoC

The opensolvers team taught OpenBLAS a new RISCV64_ZVL1024B target and ran HPL on the SpacemiT K3's 8 A100 AI cores (VLEN=1024). Results: A100 HPL goes from 15 to 35.9 GFLOP/s, and an equal 8+8 X100+A100 mix reaches 57.5 GFLOP/s — beating the X100-only baseline of 53.2. Full benchmark tables, the /proc/set_ai_thread affinity mechanism, and the VLEN-migration SIGSEGV pitfall, annotated.

ESWIN Computing Passes HKEX Listing Hearing — the Path to the First Publicly Listed RISC-V Chip Company

Beijing ESWIN Computing (奕斯伟计算) passed the HKEX main board listing hearing on Sep 21, 2026, positioning it to become the first publicly listed RISC-V-architecture chip company. Full financial trajectory from the prospectus coverage: revenue ¥17.52亿 → ¥20.25亿 → ¥24.31亿 (2023–2025), Q1 2026 ¥4.94亿 (+18.4% YoY), compute products jumping from ¥375K to 45% of quarterly revenue in three years, and the risk register behind the 'RISC-V first stock' label.

After RVA23: CFI, the Three Matrix Extension Routes, and What RVA23.1 Adds — Canonical's Distro View

Canonical's Jon Taylor maps the post-RVA23 RISC-V ISA landscape: Zicfilp/Zicfiss control-flow integrity with shadow stacks and landing pads, the three matrix-extension routes (VME, IME, AME) and their OS context-switch costs, runtime discovery via sys_riscv_hwprobe(), and the RVA23.1 development options that matter for distros — Ssdbltrap, Sscfg, Ssctr. Annotated with official spec links.

AIMORELOGY Ovis: CVITEK CV1842H-P Pairs Arm A53 With a RISC-V C906 at 800 MHz for Edge Vision

The Ovis AI camera module runs a CVITEK CV1842H-P: Arm A53 at 1.1 GHz plus a RISC-V C906 at 800 MHz, 1.5 TOPS INT8 NPU and 1080p AI-ISP.

OpenCL 3.1.2 Ships With Finalised Command Buffers as PoCL 7.2 Adds RISC-V Conformance

Khronos published OpenCL 3.1.2 on 18 Sep 2026 finalising command buffers; PoCL 7.2 (4 Sep) claims OpenCL 3.0 conformance on RISC-V CPUs.

CVE-2026-92518: RISC-V BPF Tailcall With Clang CFI Corrupts Kernel Stack (CVSS 7.8)

CVE-2026-92518: a RISC-V BPF tailcall bug under CONFIG_CFI_CLANG corrupts kernel stack. CVSS 7.8, fixed in 6.18.52 / 7.2.6 / 7.3-rc1.

Linux RISC-V Patch v8 Adds Zic64b and an RVA23U64 hwprobe Base Behaviour for K1, K3 and SG2044

RISC-V Linux patch v8 (20 Sep 2026) adds Zic64b to cpufeature/hwprobe and an rva23u64 base behaviour, with DT entries for SpacemiT K1, K3 and SG2044.

Ruixin Gaoguang D35: A RISC-V Dataflow Physical-AI Chip with 128 GB VRAM and >90% Compute Utilization

Suzhou Ruixin's Gaoguang D35 is a mass-produced RISC-V dataflow physical-AI chip: fully self-developed RISC-V CPU core, dedicated LPU dataflow processing unit, 128 GB on-chip VRAM, Chiplet advanced packaging, >90% compute utilization claimed, and an ISCA 2026 best-paper nomination. We annotate the architecture, the memory-wall problem it targets, and the five application scenarios.

Inside the SpacemiT K3 Preview Paper: Homogeneous Fusion, X100 + A100, and What 60 TOPS Actually Means

A technical annotation of SpacemiT's official K3 preview paper (dated 2026-01-29): the homogeneous-fusion paradigm, X100 RVA23 core microarchitecture (OpenC910 lineage, TAGE, 17-cycle L2 hit), A100 1024-bit vector + IME 1.0/2.0 matrix extensions, Linux SMP scheduling with AI-partitioned cores, and every published benchmark table — SPEC CINT2006 22.88, −5.48% under KVM, GHASH 46.6x, 3.28x memory bandwidth.

First Mass-Produced RISC-V AI Supernode Goes Live: EVAS Epoch in an Operator Data Center

EVAS Intelligence's 64-node RISC-V AI supernode — Epoch chips on E200-L liquid-cooled OAM modules in an orthogonal backplane-free fabric — is now deployed in an operator data center in Shijiazhuang, backed by a new ~RMB 2B round at a ~RMB 15B valuation. Verified facts, vendor claims labeled.

Andes AX66 Pre-Silicon: Linux KVM + Dual LLM Inference on FPGA Before Tape-Out

Andes AX66 RVA23 application core validated pre-silicon: quad-core cluster on AMD Versal VP1902 FPGA in S2C Prodigy S8-100, booting Linux KVM with two VMs and running TinyStories 42M LLMs before tape-out. Full spec tables and what the demo proves.

Andes AX66 Runs Linux KVM and Two 42M LLMs on an S2C Prodigy S8-100 FPGA Prototype

Quad-core Andes AX66 (RVA23, 13-stage, 8-wide OoO) on one AMD Versal VP1902 FPGA at 60 MHz boots Linux KVM and runs two TinyStories 42M LLMs at once.

Axelera Europa AIPU Ships: 629 TOPS at 45 W with 16 RISC-V Vector Cores, Now in Dell and Supermicro Servers

Axelera Europa AIPU ships: 629 TOPS at 45 W, 16 RISC-V vector cores, 128 MB L2, now validated in Dell XE5 and Supermicro 111AD servers.

deepin 25 Ships an RVA23 Baseline for SpacemiT K3: Offline 30B Inference on a RISC-V Desktop

deepin 25 adds an RVA23 overlay repo (GCC 15/16, Binutils 2.46, Glibc 2.42, LLVM 21/22) for offline 30B LLM inference on the SpacemiT K3.

Infineon Says Its Next-Generation Automotive MCU Family Goes All-In on RISC-V

Infineon says next-gen automotive MCUs go all-in on RISC-V, replacing the split Arm TRAVEO T2G and TriCore AURIX line-up. Ecosystem status, gaps.

RISC-V Post-Quantum Cryptography Extension v0.1 Enters Internal Review: vkeccak.vi Explained

RISC-V PQC extension v0.1 enters internal review (11-25 Sep 2026): what vkeccak.vi does, what is in the repo, and why embedded teams should watch.

MNN LLM Inference on SpacemiT K3 — IME2 W4B64 Quantization and Benchmarks

Alibaba MNN on SpacemiT K3 RISC-V: end-to-end LLM inference optimization using IME2 matrix extension, asymmetric W4B64 quantization, TCM double-buffer pipelining. Benchmarks, build flags and source code references.

A 28nm RISC-V Out-of-Order Core Designed by Agents: Inside Cuisi's 6nm Inference Chip Plan

Shanghai Cuisi raised a nine-figure RMB angel round after a 28nm RISC-V out-of-order tape-out built on its agentic EDA flow. Next: 6nm.

Aowei Lingxin RV9000 Boots: Modular RISC-V + DSA Heterogeneous SoC, Up to 24 Cores

The RV9000 RISC-V + DSA heterogeneous SoC completed tape-out and bring-up: 4 or 8 general cores plus up to 16 SDPA accelerators, NoC interconnect.

JetKVM Mini Drops Linux for the ESP32-P4X: A $39 RISC-V KVM-over-IP at 400 MHz

JetKVM Mini swaps a Rockchip Linux SoC for an ESP32-P4X RISC-V MCU: 400 MHz dual-core, 32 MB PSRAM, 1080p30 capture, from $39 in October.

OpenSBI Adds SpacemiT K3 Platform Support: 8 × X100 and 8 × A100 Harts with Mixed VLEN

OpenSBI patch v4 adds SpacemiT K3 support: eight X100 and eight A100 harts, 256-bit vs 1024-bit VLEN, booted to a Linux 7.3-rc1 shell.

SiFive + AMD ROCm on BigSky — RISC-V Head Node Gets Its Second GPU Stack

SiFive and AMD demonstrated AMD ROCm 10.0 running on the BigSky SF-2U870 datacenter development platform at AI Infra Summit 2026: 32 P870-D RISC-V cores as head node, AMD Radeon AI PRO R9700 GPUs driving inference offload, running the Gemma4-E2B LLM. Full hardware spec tables, the ROCm demo stack, and how it compares with NVIDIA's CUDA port.

AMD ROCm 10.0 Runs on the SiFive BigSky SF-2U870: 32 P870-D Cores as a RISC-V AI Host

SiFive and AMD demoed ROCm 10.0 on the 32-core P870-D BigSky SF-2U870 RISC-V server, running Gemma4-E2B with Radeon AI PRO R9700 offload.

Infineon Maps RISC-V for Automotive Zone Controllers at Hot Chips 2026 — MCU Island + MPU Island, AUTO-SIG Profiles, and the Three-Architecture AURIX Portfolio

Infineon's Hot Chips 2026 automotive RISC-V architecture talk: zonal E/E architecture transition, MCU island + MPU island heterogeneous zone controllers, RVI AUTO-SIG profiles (RV32E+I+M+U baseline), RVM virtualization for mixed criticality, and the three-architecture AURIX portfolio (TriCore + Arm + RISC-V).

Aheesa VIHAAN-I: A RISC-V Broadband SoC Moves From First-Pass Silicon to Packaging Partner

Aheesa's RISC-V broadband SoC VIHAAN-I goes from first-pass silicon to an Optilink packaging MoU, targeting commercial deployment in early 2027.

Axelera Voyager 1.8 Swaps GNU newlib for LLVM 20 on RISC-V: 10x Smaller Wheels, ~10% Faster Small-Model Inference

Voyager 1.8 replaces GNU newlib with LLVM 20 on Axelera's RISC-V toolchain: wheel drops ~200 MiB to ~20 MiB, up to ~10% faster small-model inference.

EU Cyber Resilience Act Article 14 — 24-Hour Vulnerability Reporting Hits RISC-V IoT

EU CRA Article 14 reporting obligations live Sept 11 2026. 24-hour vulnerability reporting clock, ENISA Single Reporting Platform, €15M / 2.5% global turnover penalty tier, SBOM and CE marking by Dec 11 2027. Scope across all RISC-V MCU, SoC and IoT products shipping into the EU.

Fedora 45 RISC-V Rebuild: GCC Internal Compiler Errors on SpacemiT K1 and K3 Boards

Fedora's RISC-V group reports GCC ICEs on SpacemiT K1/K3 boards linked to new glibc vector optimisations, while the F45 rebuild stays on track.

XuanTie Edge AI Solution: Titan 512–4096-bit Vector Engine and a Programmable RISC-V Scheduling Core

DAMO XuanTie's edge AI solution pairs a RISC-V scheduling core with a 512/1024/4096-bit Titan vector engine, 66 vector instructions and 177 operators.

Nuclei Tech (芯来科技) Files for IPO — Global First ASIL-D RISC-V Automotive CPU IP

Nuclei Technology files for BSE IPO. Global first RISC-V CPU IP certified to ISO 26262 ASIL-D. NA900 automotive IP, UX1030H RVA23 high-performance core, 300+ customers, 87% gross margin, 4.85B cash.

Rust on RISC-V 2026: Tier 2 with Host Tools + the New riscv64a23 Target

A snapshot of Rust's RISC-V platform support as of September 2026: which targets are stable, which is new, and why the Tier 1 RFC is still open. Practical build instructions and toolchain notes for production Rust on RISC-V hardware.

RISC-V Server Chips Enter Production Datacenter: LX500, K3 & JH-B100

RISC-V server silicon moves from lab to production racks. Deep dive into BlueChip LX500, SpacemiT K3, and StarFive JH-B100 — the three chips that target the data center.

YuzukiNeko Brings Allwinner F101 and a T-Head C907 Core to a Raspberry Pi Pico–Sized Linux SBC

Allwinner's F101 SoC — one 1.008 GHz T-Head C907 RISC-V core, 8–16MB SiP PSRAM — runs mainline Linux 7.2 and Zephyr on a 51×21 mm Pico-sized board.

CONVOLVE's Chimera Chip: RISC-V Host Plus Memory-Centric and Neuromorphic Accelerators

TU/e's EU-funded CONVOLVE project taped out Chimera: RISC-V cores plus memory-centric and neuromorphic accelerators, validated on fabricated silicon.

Espressif ESP32-P4X-EYE Puts a 400 MHz Dual-Core RISC-V Vision Kit in a Camera Shell

Mouser stocks Espressif's ESP32-P4X-EYE: a camera-shaped kit on the dual-core 400 MHz RISC-V ESP32-P4 with up to 32MB PSRAM and H.264.

NanoCore 3D-CIM: RISC-V Heterogeneous Compute-in-Memory Chips Near Mass Commercialization

Hangzhou NanoCore closed a ¥1B C1 round for 3D-CIM AI inference silicon combining DRAM near-memory, SRAM CIM and RISC-V. TOPS and node undisclosed.

Nuvoton NPCR1 OpenTitan RISC-V Secure MCU Lands in Antmicro's Renode Simulation Framework

Nuvoton's NPCR1 OpenTitan RISC-V secure MCU is simulatable in Antmicro's Renode, targeting FIPS 140-3 Level 1 and Common Criteria PP0084.

Waveshare ESP32-C5 Pico: Dual-Band Wi-Fi 6 RISC-V Board in Pico Form Factor From $8.99

Waveshare's ESP32-C5 Pico puts Espressif's 240 MHz RISC-V Wi-Fi 6 + 802.15.4 SoC on a Pico board. Specs, variants, pricing and toolchain.

SemiFive Starts Mass Production of HyperAccel Bertha: A >500 mm² 4nm Inference Accelerator

SemiFive starts mass production of HyperAccel's Bertha LLM inference chip on Samsung 4nm. Die area, schedule, contract terms, and the unconfirmed ISA.

SJTU IPADS SPMP Ratified into RISC-V ISA — First China-Led ISA Extension in RISC-V’s 11-Year History

RISC-V International's Board of Directors approved the SJTU IPADS-led SPMP extension on Aug 31, 2026 — the first ISA extension defined end-to-end by a Chinese team in RISC-V's 11-year history. Deep dive on Supervisor Physical Memory Protection: motivation, encoding, hardware model, deployment on XiangShan and Nuclei.

Andes Cut a RISC-V LSU Customization From 8.5 Weeks to 6 Using ChipAgents — Here Are the Numbers

Andes used ChipAgents' agentic AI on a RISC-V LSU customization and a BIU verification flow. The reported numbers, and the caveats.

Design IP Hit $9.45B in 2025: CPU IP Took 43%, and Royalties Outgrew Licensing

SemiWiki's 2025 design IP tally: $9.45B market, CPU IP 43% share, royalties up 16.1% versus licensing up 10.7%. Where RISC-V's opening sits.

Haawking HX2000: The RISC-V DSP Line Behind a Fresh Series B — And What Still Isn't Published

Zhongke Haoxin closed a Series B for its Haawking HX2000 RISC-V DSP line. Verified facts, segment context, and the specs still missing.

RISC-V Matrix Extensions in 2026: IME, VME and AME, Plus the VME Ratification Dates

IME, VME and AME are RISC-V's three matrix tracks. What each does, where they stand, and the VME freeze and ratification dates for 2026.

YiXing Intelligence Raises ¥1.5B to Scale Its Epoch RISC-V Cloud AI Chip and ELink Superpod

YiXing Intelligence closed a ¥1.5B Series B led by Beijing state funds to mass-produce the Epoch RISC-V cloud AI chip. Verified facts and open gaps.

CPython Officially Adds RISC-V as Tier 3 Platform — First Open ISA in Python’s Support List

CPython now officially supports RISC-V as a PEP 11 Tier 3 platform. RISE Project provides buildbots, PyTorch wheels land on riscv64. Technical deep dive on what Tier 3 means, the roadmap to Tier 2, and the ecosystem gap.

Automotive RISC-V Control Chips Get Two Competing Rulebooks: Quintauris RT-Europa and the China SAE Specification

Two automotive RISC-V control-chip specs move in parallel: Quintauris RT-Europa and a China SAE standard covering lockstep, ASIL-D and HSM.

ESWIN EIC7700 Was the Hardware Behind the HICOOL 2026 RISC-V + AI Challenge — And a 13.3 TOPS vs 19.95 TOPS Discrepancy

ESWIN's EIC7700 board powered the HICOOL 2026 RISC-V+AI final. Here are the verified SoC specs — and why two different TOPS figures are circulating.

SpacemiT K1 and K3: What Landed Upstream in August 2026 — Kernel, Triton, llama.cpp and Toolchain

SpacemiT August 2026 upstream report: K3 display, UFS and PCIe patches in review, Triton merged into FlagTree, glibc 2.44 and GDB 17.2.

SpacemiT K1 Runs ONNX Runtime int4 LLM via IME Matrix Extension

SpacemiT K1 achieves ~80ms/token int4 LLM inference with ONNX Runtime by leveraging the X60 core's IME matrix extension. Technical deep dive on MatMulNBits, quantization, and performance tuning.

Lingxu Smart P100: China's First Dynamic SMT4 RISC-V Server CPU

Lingxu Smart P100 is China's first server-class dynamic SMT4 RISC-V CPU core, engineered for the agentic-AI era. Deep dive into SMT1->SMT4 dynamic switching, 20-stage OoO pipeline, 8-decode/10-issue, TAGE branch prediction, SPEC CPU2006, hardware RAS auto-recovery, test chip tape-out Aug 2026.

Axelera AI Europa: 629 TOPS at 45 W with 16 RISC-V Vector Cores on Samsung Foundry FinFET

Axelera AI's Europa pairs eight 2nd-gen AI PUs with 16 RISC-V vector cores: 629 TOPS at 45 W, 128 MB L2 SRAM, on Samsung Foundry FinFET.

DeepComputing DC-ROMA RISC-V Mainboard III Enters Production: SpacemiT K3, 60 TOPS, First RVA23 Laptop Board

DeepComputing's DC-ROMA RISC-V Mainboard III enters production on SpacemiT K3 with 60 TOPS, claiming the first RVA23 laptop mainboard.

Micro Magic MagicV: A 5 GHz, 13,000 CoreMark 64-bit RISC-V Core Running Linux, Zephyr and FreeRTOS

Micro Magic's MagicV 64-bit RISC-V cores claim 5 GHz and 13,000 CoreMarks, 200 mW per core, with Linux, Zephyr and FreeRTOS support.

openKylin 3.0 Moves to Linux 7.0 with RVA23 Support: 36.5x FP16 Inference Gain from RVV Optimisation

openKylin 3.0 moves to Linux 7.0 with GCC 15, glibc 2.42 and LLVM 22, adds RVA23, and reports 2-5x FP32, up to 36.5x FP16 RVV gains.

Qualcomm Dragonwing Q-2390 and IQ-2390: A Real-Time RISC-V MCU Inside a Mainstream IoT SoC

Qualcomm's Q-2390 and IQ-2390 pair a quad-core Kryo CPU and Adreno 704 GPU with a real-time RISC-V MCU, running Linux, Android and Zephyr.

XCENA MX1: 3,072 RISC-V Cores on a CXL Computational-Memory Card

Deep dive into the XCENA MX1 computational-memory device: 3,072 RISC-V cores, Samsung 4nm, 2TB DDR5, CXL 3.2, vector search and near-data processing. Hot Chips 2026 analysis.

GigaDevice GD32VW553: RISC-V Dual-Mode Wi-Fi 6 + BLE 5.2 MCU

GigaDevice GD32VW553 is a Nuclei N307 32-bit RISC-V wireless MCU with integrated 2.4 GHz Wi-Fi 6 (802.11ax OFDMA + MU-MIMO) and Bluetooth LE 5.2 radio, 4 MB Flash, 320 KB SRAM, hardware AES/DES/Hash/PKCAU/TRNG, Matter-over-Wi-Fi certified. QFN32/QFN40, -40 to 105 °C.

GigaDevice CCRC4XXX: First Post-Quantum RISC-V Automotive AI MCU

GigaDevice CCRC4XXX automotive AI MCU pairs CRV6 RISC-V cores with native post-quantum crypto (PQC), on-chip NPU, and Evita-Full HSM. Full spec deep-dive plus China's first RISC-V vehicle-control-chip standard from the Suzhou Automotive Summit.

Zhongda Tech K3 Industrial Edge AI Module: 60 TOPS RISC-V on Mini COM-E

Zhongda Tech's SpacemiT K3-based industrial edge AI module delivers 60 TOPS in a Mini COM-E form factor. 8 X100 cores, 8 A100 AI cores, 30B LLM inference, -40 to 70°C, all-domestic supply chain.

SiFive BigSky SF-2U870: First Rackable 2U RISC-V Datacenter Server

SiFive BigSky SF-2U870 is the world's first enterprise-grade rackable 2U RISC-V server. Deep dive into P870-D cores, DDR5-5600, PCIe Gen5, NVMe, and CUDA/NVLink Fusion support.

CH32X035: All-in-One USB + Type-C PD RISC-V MCU from WCH

WCH's CH32X035 is the first QingKe RV32IMAC MCU with integrated USB 2.0 + USB PD + Type-C PHY, PIOC programmable I/O controller, dual OPA, triple CMP, 12-bit ADC and 65 KB Flash — collapsing any external PD trigger chip.

Andes RVBuilder: AI-Assisted RISC-V IDE for VS Code

Andes RVBuilder brings RISC-V toolchain management, debugging and MCP-based AI assistance into Visual Studio Code. Cross-platform for Windows and Linux.

StarFive Dubhe-100: First Deliverable Server-Grade RISC-V HPC CPU IP

Timesintelli PT153S: Fully Domestic RISC-V Gigabit USB Ethernet Controller

Technical deep dive into Timesintelli PT153S, a fully-domesticated RISC-V (RV32IMAC) USB 3.2 Gen1 to Gigabit Ethernet controller chip that shipped over 1M units in three months.

HPMicro HPM53M1: RISC-V MCU for Robot Joint Control

Technical deep dive into HPMicro HPM53M1, a 480MHz RISC-V MCU with integrated 150V motor drivers, 4x CAN-FD, and 2MSPS ADC designed for robot joint servo control.

SpacemiT K3 Pico-ITX: Compact 60 TOPS RISC-V AI Computer

Technical overview of SpacemiT K3 Pico-ITX, a 2.5-inch Pico-ITX plus SBC built around the 60 TOPS RVA23 K3 AI CPU with 10GbE, NVMe, and dual M.2 expansion.

SpacemiT K3: Flagship RISC-V AI CPU Deep Dive

Technical deep dive into SpacemiT K3, the world's first RVA23 mass-production RISC-V AI CPU: X100 cores, A100 AI engines, 60 TOPS, and four claimed world-first features.

myCobot 280 RISC-V: World's First RISC-V Full-Stack Open-Source Robot Arm

Deep dive into the myCobot 280 RISC-V, the world's first 6-axis collaborative robot arm powered by the SpacemiT K1 RISC-V AI CPU with full-stack open-source design.

XiangShan + Ruyi: China's Open RISC-V Processor System and Native OS

Deep dive into XiangShan Kunming Lake open-source RISC-V processor and the Ruyi native operating system for RISC-V.

CH32H417: WCH's Dual-Core 400MHz RISC-V MCU with USB 3.0 5Gbps

中科通量金刚GC3: RISC-V + Dataflow Architecture for Video AIGC

Deep dive into the 金刚GC3 chip by 中科通量: 12 RISC-V cores, 200 TOPS INT8, 128GB LPDDR5 ECC unified memory, dataflow architecture designed for video generation and understanding.

SiFive Performance P570 Gen 3: Data-Center-Grade RISC-V IP

CH32V407/467: 200MHz RISC-V with Dual USB HS, Ethernet PHY, and RVV

CH32V003: The $0.1 RISC-V MCU Getting Started Guide

CH32V317 Deep Dive: USB 2.0 HS + Ethernet PHY on a Single RISC-V Chip

SpacemiT K1 OpenWrt SDK: Complete Development Guide

K3 RVA23 Architecture: Why It Matters for RISC-V

MounRiver Studio: The IDE for WCH RISC-V Development

K1 AI SDK: Running ML Models on RISC-V Hardware

RISC-V vs ARM in 2026: The Real Ecosystem Gap

Building an Industrial Gateway with CH32V307

Canonical Sets Enterprise Target for Open-Source RISC-V — Ubuntu at Hot Chips 2026

Canonical outlines Ubuntu's enterprise RISC-V strategy at Hot Chips 2026: RVA23 baseline, 95% package parity, native builders, Kubernetes/MicroCloud porting, and RISE Project collaboration.

Epic Semi Contrail AIX: First RISC-V “AI Execution Platform” with 32 Cores + 75 TOPS

Deep dive into Epic Semi Contrail AIX: 32 server-class RISC-V scalar cores + 16 integrated AI cores, up to 75 TOPS (INT8), RVA23, RVV 1.0 + VME, DDR5-6400, PCIe Gen5, CXL 2.0, hypervisor + AIA 1.0. Built for the Agentic AI Era.

MIPS Launches Acies, Actus & Aegis — Three RISC-V Platforms for Physical AI

GlobalFoundries-owned MIPS unveils three workload-native RISC-V platforms for physical AI: Acies for edge inference, Actus for real-time control, Aegis for safety-critical systems. Software-first design with class-leading tokens-per-watt.

NVIDIA Defines RISC-V as Third Server CPU for CUDA & NVLink Fusion at Hot Chips 2026

At Hot Chips 2026, NVIDIA laid out concrete requirements for RISC-V host CPUs to join its CUDA and NVLink Fusion stacks. RVA23, Boot & Runtime Services, ACPI 6.6, PCIe coherence, and peer-to-peer are mandatory. SiFive named as first RISC-V NVLink Fusion CPU partner.

Ruixin High-Beam D35: World's First RISC-V Dataflow Physical AI Chip Enters Mass Production

Suzhou Ruixin launches High-Beam D35, the world's first mass-produced RISC-V dataflow architecture physical AI chip. 128 GB memory, self-developed RISC-V CPU core recognized by Intel, ISCA 2026 best paper nominee. Technical deep dive on dataflow computing, physical AI applications, and ecosystem strategy.