Table of Contents
Published: 2026-09-14 · Category: RISC-V MCU · Reading time: ~4 min · Status: DRAFT
A second source for broadband silicon
Aheesa Digital Innovations, a Chennai-headquartered fabless company backed under India's Design Linked Incentive (DLI) scheme, has signed a memorandum of understanding with Optilink Networks covering packaging for VIHAAN-I, its RISC-V broadband networking SoC. Optilink — a Mumbai OEM founded in 2005 that designs and manufactures FTTH, IP-TV and IP networking hardware — had already supported the programme through testing, validation and engineering.
Under the MoU, Optilink takes on end-to-end product development from prototyping through packaging, and the two companies work toward qualifying and commercialising ONT/CPE products based on the VIHAAN-I chipset. Aheesa states it is now moving toward commercial deployment in early 2027.
For procurement teams, the significance is supply-chain rather than performance. Home-gateway silicon is a category with very few viable suppliers and very long product lifetimes. A credible additional RISC-V-based option — designed in one country, packaged and integrated by an established CPE manufacturer in the same country — is exactly the kind of second source that open-ISA architectures are supposed to make possible.
What was actually achieved on silicon
The company's stated milestones, in order:
- Tape-out on Republic Day 2026 (26 January).
- Investment from the Tamil Nadu Infrastructure Fund Management Corporation via the Tamil Nadu Emerging Sector Seed Fund.
- First-pass silicon success on Independence Day (15 August 2026) — the chip worked on the first manufacturing attempt.
First-pass silicon success is a genuine result and worth stating plainly: a respin costs months and a mask set. But note what it does not tell you. It confirms the design behaves as specified electrically. It says nothing about yield at volume, thermal behaviour under sustained load, or signal integrity across production variance — all of which are the usual failure modes between a working prototype and a shippable product.
What is not disclosed
This is where the announcement is thin, and it is worth being blunt about it. The published material contains no core count, no clock frequency, no process node, no foundry, no power envelope, no memory configuration, and no RISC-V profile or extension string. We do not know whether VIHAAN-I targets an RV32 or RV64 base, whether it implements RVA22 or RVA23, or whether it carries vector or crypto extensions. We do not know which interfaces it integrates — PON MAC, Ethernet PHY, switching capacity or USB are all unspecified in the material available.
Any of those numbers you see quoted elsewhere for this part should be treated as unverified until Aheesa publishes a datasheet.
The software question is the real risk
For a broadband SoC, silicon is the easier half. An ONT or CPE device ships with a firmware stack — typically a vendor SDK layered over Linux or an RTOS — plus TR-069/TR-369 management, QoS, VLAN handling, and operator-specific customisations that vary per ISP. The integration risk is concentrated entirely in that layer.
Aheesa's approach, per its founder and CEO Sridharan Mani, has been to involve OEMs from the design stage so the chip is validated against specific customer applications before fabrication. That is a sound strategy for de-risking the first tape-out, and it plausibly explains the first-pass success. It also creates a dependency: if an OEM changes its software stack or power-management profile after tape-out, Aheesa may need an engineering change or a new silicon revision.
Optilink's role matters here. Two decades of FTTH hardware and firmware experience is precisely the capability that turns a validated die into a carrier-qualifiable product, and packaging-and-integration partnerships are the conventional route by which fabless startups bridge that gap.
Ecosystem context
The announcement sits inside India's Semicon 2.0 programme, notified with a total outlay of ₹1,27,500 crore across six pillars: chip design, machines and materials, new fabs, ATMP/OSAT, R&D, and talent development. The India Electronics and Semiconductor Association welcomed the notification on 1 September 2026, citing policy continuity as the key enabler for ten-to-fifteen-year investment horizons.
That is the frame worth watching. Broadband CPE is a long-lifecycle, high-volume, cost-sensitive market — a poor fit for a startup chasing premium margins, and a reasonable fit for a design house building a durable second source on an open ISA with no per-core licensing cost.
Engineering takeaway
Do not design VIHAAN-I into anything yet — there is no datasheet and no published availability. Do watch it. The signal to act on is the combination of first-pass silicon plus a credible manufacturing and integration partner plus a stated early-2027 commercial window. If a datasheet appears with a disclosed profile and interface set, this becomes a legitimate option for teams looking to diversify broadband silicon supply away from a single incumbent architecture.
Sources
- DataQuest (DQIndia) — "From silicon to scale: Aheesa signs packaging MoU with Optilink Networks" — https://www.dqindia.com/semiconductors/from-silicon-to-scale-aheesa-signs-packaging-mou-with-optlink-networks-12506841
- CELLIT — "From Silicon to Scale: Aheesa Signs Packaging MoU with Optilink Networks" (same press release) — https://cellit.in/from-silicon-to-scale-aheesa-signs-packaging-mou-with-optilink-networks
- MTI News — "Semicon 2.0 Strengthens India's Semiconductor Flywheel; IESA Sees Major Investment Opportunity", Mumbai, 1 September 2026 — https://mtinews.in/semicon-2-0-strengthens-indias-semiconductor-flywheel-iesa-sees-major-investment-opportunity
Verification notes
- Publication date not confirmed. Neither the DataQuest nor the CELLIT page displayed a publication date in the retrieved content. Internal evidence (Semicon 2.0 notification in July 2026, Independence Day first-silicon on 15 August 2026) places the MoU in early September 2026. This is stated as "early September" rather than a precise date.
- The DataQuest and CELLIT items are the same press release reproduced by two outlets — they are not independent corroboration of each other. No third-party technical coverage was found.
- No specifications were invented. Core count, frequency, process node, foundry, power, memory, interfaces and ISA profile are all not disclosed by the sources and are listed as such in the body.
- A separate cluster of aggregated blog posts circulating from 28 August 2026 claims a ~US$10 million raise and volume production by end of Q1 FY2027. These appear only on syndicated live-blog mirror sites and were deliberately excluded; the "early 2027" commercial target used here comes from the primary press release.
- The Semicon 2.0 outlay figure (₹1,27,500 crore) is consistent across both the IESA/MTI News item and the Aheesa release.
- Political framing was deliberately avoided. The draft uses only "open standard / multi-source supply / long-lifecycle availability" positioning, per site editorial policy.