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RISC-V Development

YuzukiNeko Brings Allwinner F101 and a T-Head C907 Core to a Raspberry Pi Pico–Sized Linux SBC

2026-09-09 6 min read EN
RISC-V Development

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Status: DRAFT — not published Date: 2026-09-09 Category: RISC-V Development Tags: Allwinner F101, XuanTie C907, YuzukiNeko, SBC, Linux 7.2, Zephyr, PSRAM, MIPI DSI Meta description: Allwinner's F101 SoC — one 1.008 GHz T-Head C907 RISC-V core, 8–16MB SiP PSRAM — runs mainline Linux 7.2 and Zephyr on a 51×21 mm Pico-sized board. Reading time: ~6 min

A Pico-sized board that runs mainline Linux

YuzukiHD has published YuzukiNeko, an open-source-hardware single board computer built around Allwinner's F101 SoC. The headline claim is form factor plus a real kernel: the board measures roughly 51 × 21 mm — Raspberry Pi Pico territory — and runs a mainline-based Linux 7.2 tree rather than a vendor fork. Schematics, EasyEDA PCB layout, Gerber files, a 3D STEP model and the BoM are all published, so the design is reproducible rather than just documented.

For engineers who have spent time fighting vendor BSP kernels on small RISC-V parts, "mainline-based" is the part worth reading twice.

What is inside the Allwinner F101

The F101 is positioned by Allwinner as a "Smart Control and Display Processor," and the peripheral mix reflects that: it is a display-driver SoC with a CPU attached, not an application processor.

The PSRAM-in-package decision is the defining engineering trade. There is no external DDR bus, no DRAM routing constraints and no DDR PHY to bring up — which is exactly what makes a 51 × 21 mm four-layer-friendly board possible. The cost is that 8–16 MB is a hard ceiling, and it is PSRAM rather than SDRAM, so bandwidth and self-refresh behaviour differ from what you would plan for on a DDR2/DDR3 part.

Display and multimedia blocks

The F101's reason for existing is driving panels:

That resolution envelope targets industrial HMIs, serial display modules and smart-home panels — not video playback appliances.

Board-level I/O

YuzukiNeko keeps the carrier minimal:

On the SoC side: SDIO 2.0/3.0, 2 × SPI, 6 × UART, 3 × TWI (I2C), 4-channel PWM plus 2 × PWM_BL, IR_RX, 1-channel GPADC and 4-channel TPADC. Audio out is available as analog HPOUT or digital I2S/PCM and OWA OUT.

Six UARTs and four PWM channels on a part this small is a genuinely useful combination for industrial control and multi-drop serial work.

Software: Linux 7.2, Buildroot and Zephyr

Three repositories back the board:

Having both a mainline-ish Linux path and a Zephyr path on the same silicon is unusual at this size. Practically, it lets you prototype on Linux and then move a deterministic control loop to Zephyr without changing silicon — a useful hedge for teams that need a long-term, multi-source supply position on a stable open standard rather than a single-vendor lock-in.

One number to treat with care

There is a published discrepancy on the CPU clock. CNX Software's board write-up and the Whycan product brief both list the C907 at 1.008 GHz. Allwinner's own F101 hardware design guide (document version 0.90, explicitly marked as based on a design that is complete but not yet production-validated) lists all three F101 variants at 600 MHz, and additionally documents an F101S4 part with 32 MB PSRAM that does not appear in the other sources.

Do not size a thermal or performance budget around 1.008 GHz until a production datasheet resolves it. Treat 600 MHz as the conservative planning figure.

Availability and price

YuzukiNeko is not for sale yet. A Whycan forum participant reports the F101 at 18 yuan (roughly US$2.70); board pricing has not been announced. YuzukiHD's earlier open-source hardware — the Avaota A1 and Yuzuki Chameleon — did reach retail, which is a reasonable precedent but not a commitment.

Not disclosed by the sources used here: power consumption figures, process node, PSRAM bandwidth, and any benchmark results.

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com