Andes AX66 Runs Linux KVM and Two 42M LLMs on an S2C Prodigy S8-100 FPGA Prototype

Published: 2026-09-18 · Category: RISC-V Datacenter · Reading time: ~5 min · Status: DRAFT

What was actually shown

At the AI Infra Summit (Santa Clara Convention Center, 15–17 September 2026), Andes Technology demonstrated its AndesCore AX66 running live on S2C's Prodigy S8-100 prototyping system at booth #1704. The announcement that names the setup was published by S2C on 17 September 2026, alongside S2C being named Andes' 2026 Partner of the Year.

The demo is a quad-core AX66 cluster mapped onto a single AMD Versal Premium VP1902 FPGA inside the S8-100. Two operating points are given: it runs at 60 MHz and uses approximately 55% of the FPGA's logic capacity. On top of that, two software workloads:

• Linux KVM virtualisation — a hypervisor environment hosting two separate virtual machines.
• Live AI inference — two large language models simultaneously, specifically TinyStories 42M (Llama 2 architecture), inside the virtualised environment.

The AX66 microarchitecture on the record

Andes describes the AX66 as its flagship 64-bit RISC-V application processor IP, RVA23-profile compliant. The published parameters:

That combination — RVA23 plus hypervisor with AIA plus CHI-based clustering — is the specific configuration that makes a virtualised multi-OS demo feasible at all. RVA23 makes the vector and hypervisor extensions mandatory, so a compliant core is expected to carry both; AIA is what lets a hypervisor route interrupts to guests without heavy emulation. The demo is essentially a check that those pieces are real in RTL, not just in the datasheet.

Why pre-silicon, and why 60 MHz

The value proposition is about calendar time, not performance. SoC teams selecting a high-performance core normally have to wait for first silicon to answer questions like: does our custom instruction extension survive a full Linux boot? Does the hypervisor actually schedule two guests? Does our accelerator driver work in a virtualised environment?

On an FPGA prototype those questions get answered months earlier. S2C's VP of engineering, Ying Chen, frames it directly: prototyping is "where critical software and architecture decisions are proven early," not a late-stage verification step.

The 60 MHz figure needs to be read correctly. FPGA prototyping clocks are typically one to two orders of magnitude below the target ASIC frequency. This is a functional and architectural validation platform, and no performance claim should be drawn from it. Andes does not publish an AX66 target frequency in this announcement; the appropriate entry for that field is not disclosed here.

The ~55% logic utilisation number is the more informative engineering datum. It says a quad-core cluster plus its coherency fabric leaves roughly 45% of a VP1902 free for customer logic — accelerators, custom extensions, I/O models. That is the headroom number a team sizing a prototype would actually ask for.

Custom extensions are the point

The announcement names the underlying use case explicitly: validating Andes Custom Extension (ACE) instruction-set extensions and hardware accelerators by booting the full software stack — hypervisor included — before tape-out.

This is where an open ISA earns its keep in a commercial flow. A custom extension is only useful if a compiler, an OS and a hypervisor can all be built against it and still run real workloads. Running two concurrent LLMs under KVM is a deliberately unglamorous stress case: it exercises context switching across guests, vector state save/restore, interrupt routing through AIA, and the memory system under two competing working sets.

Wider context of the collaboration

The award reflects activity across the year, not just this demo. S2C's own materials state that Andes IP including AX45MPV and AX66 has been brought up on the S8-100 for Linux and edge-AI demos, that the S8-100 has roughly 100 million gates of equivalent single-system logic capacity with multi-FPGA expansion, and that the two companies have shown jointly at RISC-V Now! by Andes 2026 (Hsinchu, San Jose, Beijing, Shanghai), COMPUTEX 2026, the RISC-V North America and China Summits, and DVCon in the US, Japan and Taiwan.

The same demo is scheduled to appear at the RISC-V China Summit, 18–20 October 2026.

Engineering takeaway

The datapoint worth keeping is not the 60 MHz or the two 42M models — both are small. It is that an RVA23-class, 8-wide out-of-order RISC-V core now has a commercially supported pre-silicon path that boots Linux, a hypervisor, two guests and a concurrent AI workload. For a team designing a custom SoC, that compresses the architecture-decision loop from "wait for silicon" to "run it this quarter."

If you are evaluating the AX66, the questions to put to Andes are the ones this announcement does not answer: target frequency at a given process node, area and power, and what the same cluster does at ASIC speed.

Sources

• S2C / Andes Technology — "S2C Named Andes Technology's 2026 Partner of the Year", San Jose, Calif., 17 September 2026 — https://www.andestech.com/en/2026/09/18/s2c-named-andes-technologys-2026-partner-of-the-year
• Andes Technology — "Andes Technology Honors Quintauris as 2026 Partner of the Year", Munich, 15 September 2026 (background on Andes' RVA23 / automotive positioning) — https://www.andestech.com/tw/2026/09/15/andes-technology-honors-quintauris-as-2026-partner-of-the-year-2/
• S2C China — Chinese-language account of the same award and the AI Infra Summit demo, September 2026 (source for S8-100 ~100M-gate capacity, AX45MPV/AX66 history, exhibition list, RISC-V China Summit plans)

Verification notes

• Every figure — quad-core AX66, single AMD Versal Premium VP1902, 60 MHz, ~55% FPGA logic, two VMs under Linux KVM, two concurrent TinyStories 42M (Llama 2 architecture) models, 13-stage / 4-wide decode / 8-wide OoO, Vector + Vector Crypto, Hypervisor extension with AIA, multi-cluster over CHI, booth #1704, AI Infra Summit 15–17 Sept 2026 at Santa Clara Convention Center — is quoted from the 17 September 2026 S2C/Andes announcement.
• AX66 target frequency, process node, area and power are not published in this announcement and are therefore listed as not disclosed, not estimated.
• 60 MHz is an FPGA prototype clock. The draft states explicitly that no performance conclusion should be drawn from it. This is the most likely figure to be misread.
• The ~100 million gate S8-100 capacity figure and the exhibition/roadshow list come from S2C's own Chinese-language post, not from the Andes English release. They are attributed as such in the body and are vendor claims.
• The S2C Chinese post and the Andes English release describe the same partnership and the same demo; they are not independent corroboration of each other.
• "TinyStories 42M" is a small research model. The draft does not present it as a production-scale inference result.
• S2C is a China-headquartered EDA vendor and Andes is a Taiwan-headquartered IP vendor; this draft frames the story purely on technical and supply-chain-neutral grounds (open standard, multi-vendor tooling, earlier architecture validation) and avoids domestic-industry framing, per house style.