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RISC-V Datacenter

Aowei Lingxin RV9000 Boots: Modular RISC-V + DSA Heterogeneous SoC, Up to 24 Cores

2026-09-16 4 min read EN
RISC-V RV9000 DSA NoC SDPA HNA Heterogeneous Network-SoC

Table of Contents

Published: 2026-09-16 · Category: RISC-V Datacenter · Reading time: ~4 min · Status: DRAFT

What "lit up" means here — and what it does not

On 15 September 2026, Shenzhen-based Aowei Lingxin reported that its RV9000 series heterogeneous SoC had completed tape-out and packaging, powered on normally, and passed core basic-module tests on the first attempt, with behaviour matching design expectations.

Be precise about what that claim is and is not. Tape-out plus successful bring-up proves the design was manufacturable and that the chip executes. It does not establish throughput, power, yield, or that any accelerator reached a target clock. The company's own next steps say as much: full functional bring-up, performance validation, SDK and operating-system porting, toolchain completion, reliability characterisation and Alpha customer sample evaluation are all listed as work still in progress.

For a procurement or architecture team, the correct status label is "silicon exists and runs." Not "evaluable."

Modular many-core: RISC-V plus DSA on a NoC

The RV9000 is described as a modular configurable many-core heterogeneous design combining RISC-V with DSA (domain-specific architecture), with compute cores interconnected over an on-chip NoC for low-latency, high-bandwidth communication.

The stated design intent is the part worth noting: one die, multiple derived product configurations. Rather than taping out a different mask set for each market, the same die is intended to be configured into different specifications, balancing compute, power and interface requirements per use case.

That is a sound strategy for mid-volume infrastructure silicon where mask costs dominate. It also means the interesting question is not "what does the RV9000 do" but "which configuration am I being offered, and which blocks are fused off."

Core configurations: 4, 8, and up to 24

Published configurations:

ConfigurationGeneral coresAccelerator coresTotal
Base4 or 8—4 or 8
Accelerated (select models)4 or 8up to 16 SDPAup to 24

SDPA — software-defined processing accelerator — is the programmable acceleration layer. The published maximum combination reaches 24 cores when 16 SDPA units are present alongside the general-purpose cluster.

Note what "software-defined" implies for your software team: a programmable accelerator is only as useful as its toolchain, and the toolchain is explicitly listed as incomplete. If you are planning around SDPA offload, plan for co-development, not for a drop-in library.

Optional HNA: network offload as a configuration choice

Buyers can optionally select HNA (hardware network processing accelerator) or SDPA depending on the network workload. That is a meaningful fork. An HNA-equipped part targets packet forwarding and terminating traffic; an SDPA-equipped part targets programmable compute offload. They are not interchangeable, and a part configured one way will not serve the other workload well.

Ask which blocks are populated in the specific SKU you are quoted. Vendors in this segment frequently quote the maximum configuration while shipping a reduced one.

Target workloads

The company names five target domains: network communications, network security, edge computing, control-plane processing, and distributed storage. Stated end equipment includes communications equipment, industrial robots, AI PCs, power equipment and storage devices.

That is a coherent list for a many-core RISC-V part with optional network offload — these are all workloads where control-plane general-purpose cores sit next to a high-throughput data path. It is also a crowded field, sitting against established network processors and against RISC-V parts already shipping into similar slots.

What is not disclosed

Almost every number an engineer would actually size against is missing. Process node: not disclosed. Clock frequency: not disclosed. Compute throughput in TOPS or DMIPS: not disclosed. Power envelope: not disclosed. Memory interfaces, SerDes or Ethernet port counts and speeds: not disclosed. Package, pin count, availability date, sampling programme and pricing: not disclosed.

None of these has been estimated here. They are simply absent from the published material, and inventing plausible values would be worse than useless to a reader doing real evaluation.

Engineering takeaway

The RV9000 is worth watching for its architecture thesis — one die, configurable into different products, mixing general-purpose RISC-V with programmable acceleration over a NoC — rather than for any measurable capability today. If you work in network infrastructure or storage controllers, the thing to request from Aowei Lingxin is not a datasheet yet; it is a configuration matrix, an SDK roadmap, and a date for Alpha samples. Until those exist, treat this as architecture watching, not sourcing.

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com