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Axelera Europa AIPU Ships: 629 TOPS at 45 W with 16 RISC-V Vector Cores, Now in Dell and Supermicro Servers

2026-09-18 5 min read EN
RISC-V Axelera AI Europa AIPU D-IMC INT4 PCIe Gen4 Qwen inference tokens per watt

Table of Contents

Published: 2026-09-18 · Category: RISC-V AI · Reading time: ~5 min · Status: DRAFT

From announcement to shipping silicon

Axelera AI has moved its second-generation Europa AI Processing Unit (AIPU) from announcement to general availability. The architecture was first unveiled in October 2025 with shipments promised for the first half of 2026; the 15 September 2026 launch confirms silicon and accelerator products are now shipping, in Eindhoven-announced form.

This draft covers the shipping configuration and the published throughput numbers. It is a separate milestone from the earlier architecture announcement.

Architecture: AI cores plus RISC-V vector cores

Europa is not a GPU. The die combines two distinct core types:

That split is the reason this part belongs in a RISC-V discussion at all. The vector cores are a real RISC-V cluster doing the work that would otherwise bounce back to the host CPU. Keeping tokenisation, image pre-processing and output post-processing on the accelerator — instead of round-tripping over PCIe — is where a lot of real-world inference latency actually goes.

Alongside: an onboard H.264 / H.265 video decoder, so camera and industrial-inspection workloads do not consume host CPU cycles.

Published specifications

ItemValue
AI cores8 × second-generation
RISC-V vector cores16
Peak compute629 TOPS (quoted at INT8 by TechPowerUp)
PrecisionINT4, INT8, INT16
TDP45 W
On-chip L2 SRAM128 MB
Memory interface256-bit LPDDR5
Memory bandwidth200 GB/s
Max memory per chipup to 64 GB (per configuration)
Host interfacePCIe 4.0 ×4
VideoH.264 / H.265 decoder onboard
ProcessSamsung 5 nm (per independent coverage)
SoftwareVoyager SDK

Three form factors and the measured numbers

Europa ships as a bare chip for custom boards, and as two cards:

Validated systems on day one: Dell XE5 and Supermicro 111AD. The wider compatibility list includes HPE, Lenovo, Advantech, Axiomtek, 2CRSi and Seco. Dell, integrator E4 Computer Engineering and Axelera are also collaborating on European AI infrastructure projects.

The sales context Axelera publishes: a pipeline exceeding $1.5 billion and more than 600 customers. Next in line is Titania, described as its first chiplet, aimed at rack-mount servers and supercomputers.

The efficiency claims, and why they need care

Axelera publishes several comparison figures, and they are not the same metric, so they should not be merged:

All are vendor-stated and none were independently reproduced in the sources found. The honest reading is: Axelera is arguing that tokens per dollar and tokens per watt — not TOPS — are the right unit for inference economics, which is a defensible position, but the multipliers are marketing figures until someone benchmarks them.

The one figure with a testable shape attached is 32.1 tok/s/W on Qwen3 8B for the Server 250p, because it names a model and a card.

Engineering takeaway

Two things make this worth tracking. First, 629 TOPS inside 45 W on a PCIe card that drops into an existing Dell or Supermicro chassis is a procurement path that does not require a new server architecture — which is often the real barrier for startup silicon. Second, the 16 RISC-V vector cores are a concrete example of the pattern that keeps showing up in AI accelerators: RISC-V as the control and data-movement plane next to a proprietary or custom matrix engine.

If you are evaluating it, benchmark your own model. The published tokens/second figures are single-model, vendor-measured, and the comparison multipliers are not independently verified.

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com