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RISC-V Development

Andes Cut a RISC-V LSU Customization From 8.5 Weeks to 6 Using ChipAgents — Here Are the Numbers

2026-09-07 6 min read EN
RISC-V Development

Table of Contents

What was announced

On 2026-09-02, ChipAgents (Santa Clara, CA) announced that Andes Technology — a Founding Premier member of RISC-V International and one of the largest commercial RISC-V CPU IP suppliers — has deployed ChipAgents across multiple processor design and verification projects. ChipAgents describes Andes as its first commercial customer and a long-term co-innovation partner.

The announcement is not a chip launch. It is a data point on where engineering time actually goes in CPU IP work, and it comes with three concrete before/after numbers.

Number 1: memory load-store unit customization — 8.5 weeks to 6

The Load-Store Unit (LSU) is the subsystem that manages memory operations. Modifying one, per the announcement, traditionally requires engineers to spend weeks tracing legacy RTL, analysing architectural dependencies, and validating correctness before new functionality can be introduced.

Reported result using ChipAgents: 8.5 weeks down to 6 weeks, described as a 30% reduction in development time, while "maintaining architectural correctness."

Note what is not claimed: no statement that the LSU met timing, area or power targets, and no statement of what fraction of the 6 weeks was still human review. A schedule reduction on an RTL modification task is only meaningful if sign-off criteria were held constant, and the announcement does not say they were.

Number 2: bus interface unit verification — 2–3 months to about 3 weeks

The second task is the more interesting one. Bus Interface Unit (BIU) verification is described as requiring extensive manual work to keep specifications and verification environments in sync, and to build tests covering concurrency scenarios.

Reported result: two to three months down to approximately three weeks.

Number 3: verification stimulus generation — 1–2 weeks to 1–2 days

The third figure is a sub-task of the second. Complex verification stimulus generation tasks that previously took one to two weeks of engineering effort were reduced to as little as one to two days.

Why verification is the number that matters

RISC-V's structural advantage is customisation: you can add the instructions your workload needs and drop the ones it does not, with no per-core licence fee standing in the way. Every vendor in the ecosystem sells some variant of that story.

The cost of that advantage lands almost entirely on verification. A custom extension is not free — it has to be specified, implemented, tested against a reference model, tested for concurrency, and tested again when the base ISA or the profile moves. Andes' own product line includes the Andes Automated Custom Extension (ACE) framework, which exists precisely because customisation generates verification debt. The company states that over 20 billion Andes-powered SoCs have shipped.

So the meaningful claim in this announcement is not "AI writes RTL." It is that the verification half of the customisation loop — the half that does not scale with headcount because it is specification-synchronisation work — is where the reported 4× to 5× reduction landed. If that holds up, it changes the economics of the custom-extension pitch that the whole RISC-V IP market runs on.

Caveats before you put this in a plan

This is a plausible early result from a named production deployment, not a benchmark. Treat it as a reason to run a bounded evaluation, not as a planning factor.

What is not disclosed

None of the following appears in the sources retrieved, and nothing is estimated here:

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com