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CONVOLVE's Chimera Chip: RISC-V Host Plus Memory-Centric and Neuromorphic Accelerators

2026-09-09 5 min read EN
RISC-V AI

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Status: DRAFT — not published Date: 2026-09-09 Category: RISC-V AI Tags: CONVOLVE, Chimera, TU/e, compute-in-memory, CGRA, neuromorphic, edge AI, ESSERC 2026 Meta description: TU/e's EU-funded CONVOLVE project taped out Chimera: RISC-V cores plus memory-centric and neuromorphic accelerators, validated on fabricated silicon. Reading time: ~5 min

Measured on silicon, not only in simulation

Researchers at Eindhoven University of Technology (TU/e) and partners have presented results from CONVOLVE, an EU-funded project that produced a chip called Chimera. The distinguishing claim is methodological: the team evaluated fabricated prototype chips rather than relying on simulation alone, running realistic AI workloads and measuring energy efficiency, throughput, latency, silicon area and application accuracy against comparable existing designs.

Results were presented at the ESSERC Conference in Spain. The coverage date is 8 September 2026.

The architecture: RISC-V host, heterogeneous accelerators

Lead researcher Manil Dev Gomony, professor of low-power digital hardware design, describes the combination directly: programmable RISC-V processors paired with specialised AI accelerators including memory-centric and neuromorphic computing techniques.

The stated motivation is data movement. Gomony frames the design around reducing traffic between memory and processing units, on the basis that data movement is a dominant energy cost in AI hardware. That is a well-established position in edge accelerator design; what CONVOLVE adds is a co-design method rather than a single new block.

Cross-layer co-design as the actual contribution

The project's core methodological claim is that the AI algorithm, processor architecture, memory system and circuit layers were optimised together rather than independently. In Gomony's framing, this lets the team trade off accuracy, programmability, processing speed, silicon area and energy consumption from the start of the design process.

The project's stated objectives were ambitious and specific: a 100× improvement in energy efficiency for edge AI processing, and a 10× reduction in design time through automated design-space exploration and SoC generation. Chimera is the hardware vehicle for those claims; the coverage retrieved does not publish how far the measured silicon got against the 100× target.

The accelerator building blocks developed under the project draw on three architectural paradigms, per the project's own periodic reporting:

On the compiler side, CONVOLVE built a front-end chain targeting both MLIR and LLVM IR, with a domain-specific compiler that lowers operations to custom RISC-V ISA accelerator extensions. The team also contributed an ONNX importer to the IREE open-source ML compiler framework.

Security work included a trusted execution environment prototype based on Keystone and the Rocket core, exploration of post-quantum cryptography schemes, and work on power side-channel extraction of neural network weights from CIM crossbars, with countermeasures under development.

Programme facts

From the European Commission's CORDIS record:

Coverage names research partners in Leuven, Delft and Zürich alongside industry partners.

Reading this correctly

This is research, not a product launch. Several things should be stated plainly:

For an engineer, the value here is the validated co-design methodology and the CIM/CGRA/neuromorphic integration pattern, not a part number. For procurement, Chimera is not a sourcing candidate.

The strategic framing from Gomony is European: an affordable, energy-efficient alternative for edge computing, aimed at keeping inference on-device rather than in remote data centres, and explicitly positioned against the energy and cooling cost of large datacenter accelerators.

Not disclosed in the sources used here: process node, die area, clock frequencies, TOPS or any throughput figure, power envelope, benchmark results, commercialisation plans, and pricing.

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com