TL;DR: CPython core developer Stan Ulbrych announced that riscv64-unknown-linux-gnu is now a PEP 11 Tier 3 supported platform for both GCC and Clang with glibc. The Python Steering Council approved the designation on August 20, it was formally added to PEP 11 on August 22, and the public announcement was made on August 24, 2026. RISC-V is the only fully open instruction set architecture in CPython’s official support list.
Table of Contents
What Tier 3 Actually Means
PEP 11 defines three support tiers with very different guarantees. Tier 3 is the entry-level designation — it is a maintenance contract, not a performance guarantee.
At Tier 3, a platform needs:
- A reliable buildbot that continuously builds and tests the platform
- At least one core developer as a named maintainer
But Tier 3 does not mean:
- Failures block a Python release (they don’t)
- There is a response SLA for fixing breakage (there isn’t)
- Every regression must be fixed before the next release
For RISC-V, the named maintainers are Stan Ulbrych (GCC configuration) and Emma Smith (Clang configuration). This means RISC-V now has a formal place in CPython’s governance process — it is no longer merely tolerated platform code.
The Hardware Behind the Support
This milestone was not achieved by merging a patch and hoping. The RISE Project (RISC-V International’s Software Ecosystem effort) provided multiple RISC-V machines to the CPython project. These machines run buildbots that catch architecture-specific bugs before they ship.
Key contributors acknowledged:
- Ludovic Henry (RISE Project) — infrastructure coordination
- Furkan Onder — architecture-specific patches
- Emma Smith — Clang configuration maintainer
- Stan Ulbrych — GCC configuration maintainer, announcement author
The Sovereign Tech Agency also funded a fellowship that supported Ulbrych’s direct work on this effort.
Why real hardware matters: Cross-compilation can produce a binary that starts up, but only native execution reveals alignment faults, atomic instruction quirks, and vector extension edge cases. The RISE buildbots provide the feedback loop that makes Tier 3 meaningful rather than a fiction.
PEP 11 Tier Comparison
| Tier | CI Testing | Maintainers | Blocks Release? | Fix SLA | Examples |
|---|---|---|---|---|---|
| Tier 1 | Every commit | All core devs | Yes | Must fix before release | x86-64 Linux GCC, AArch64 Linux GCC, macOS Apple Silicon, Windows x64 |
| Tier 2 | Reliable buildbot | ≥2 core devs | Yes | Fix or revert in 24h | AArch64 Linux Clang, Windows ARM64, WASI, x86-64 Linux Clang |
| Tier 3 | Reliable buildbot | ≥1 core dev | No | No SLA | RISC-V (riscv64), Android, iOS, FreeBSD, s390x |
Ecosystem Readiness: PyTorch, NumPy, pip
CPython is the interpreter — but the package ecosystem is the real blocker for production adoption. Here is the current state:
Package Manager
- pip 24.1+ understands
manylinux_2_39_riscv64andmusllinux_1_2_riscv64wheel tags - Packages without a riscv64 wheel fall back to building from source
- Older pip versions (<24.1) silently match older
linux_riscv64tags — always upgrade pip first
Key Packages with riscv64 Wheels
| Package | riscv64 Wheel | Source | Notes |
|---|---|---|---|
| PyTorch 2.13.0 | ✅ Yes | RISE Python Wheels | CPython 3.12–3.14t; 165,591 / 212,038 tests pass (99.998%); no RVV vectorization yet, FBGEMM/QNNPACK unavailable |
| NumPy | ✅ Yes | RISE Python Wheels | Full riscv64 wheel available |
| pandas | ✅ Yes | RISE Python Wheels | Full riscv64 wheel available |
| Most other PyPI packages | ✅ No | Build from source | Use RISE supplementary package index for popular libraries |
Caveat: PyTorch on riscv64 currently falls back to scalar code (no RVV vectorization). Quantization backends (FBGEMM, QNNPACK) are not yet available. Performance-critical workloads should benchmark before committing.
Roadmap: CI Integration → Tier 2 → Optimizations
The author outlined a clear three-phase roadmap:
Phase 1: Pre-Merge CI (Near-term)
Currently, RISC-V buildbots run after a patch is merged. The RISE RISC-V Runners initiative aims to integrate RISC-V test runners directly into CPython’s CI pipeline, so RISC-V-specific failures show up in the pull request — not in post-merge email. This is the single biggest velocity improvement for contributors.
Phase 2: Tier 2 Promotion (Medium-term)
Tier 2 requires:
- At least two core developers as platform maintainers
- More consistent buildbot coverage across toolchain variants
- A track record of low regression rates
- 24-hour fix-or-revert SLA for breakage
This is as much a social milestone as a technical one — it requires sustained maintainer bandwidth and community trust.
Phase 3: Architecture-Specific Optimizations (Long-term)
RISC-V’s modular extension model (Vector, BitManip, Crypto, Hypervisor) means a generic build leaves significant performance on the table. Potential optimization areas:
- RVV (Vector) — vectorize hot loops in the interpreter
- BitManip — optimize bit-twiddling operations
- Crypto — accelerate hash and crypto operations
- Hypervisor — enable efficient VM-based testing
This is the difference between “it runs” and “it runs well.”
Building CPython on RISC-V
For developers with access to RISC-V hardware, the build process is straightforward:
Community ask: The CPython team explicitly requests testing on real RISC-V hardware across workloads and test suites, and reporting failures on the CPython issue tracker. Testing across different RISC-V environments (both GCC and Clang toolchains) is the most useful contribution, since a single buildbot configuration misses toolchain-specific bugs.
What This Means for the RISC-V Ecosystem
Python is the lingua franca of AI/ML, data science, scientific computing, and embedded scripting. Before this announcement, RISC-V could run Python — Linux distributions shipped it, developers built it — but there was no guarantee it would keep working. Now:
- AI/ML workloads can target RISC-V with a maintained Python runtime (PyTorch riscv64 wheels already exist)
- Edge devices running RISC-V Linux can now reliably use Python for scripting and automation
- Hyperscalers evaluating RISC-V for datacenter workloads have a credible language-runtime story
- Open ISA milestone — RISC-V is the only fully open instruction set in CPython’s official support tiers, alongside proprietary-licensed x86 and ARM
The timing is not accidental. In the same week:
- SiFive launched BigSky SF-2U870, the first enterprise rack-mountable RISC-V server
- Ubuntu 26.04 LTS and RHEL 10 both ship RISC-V deployment support
- NVIDIA is porting CUDA to the architecture
- RISC-V ecosystem is projected to quadruple by 2032
Python joining this moment, even at Tier 3, signals that the open hardware movement has cleared the “experimental” label.
Official Sources
- PEP 11 — CPython Platform Support Tiers (official spec)
- CPython GitHub repository
- RISE Project (RISC-V Software Ecosystem)
- Mango Developer: CPython Adds Official RISC-V Support
- Gosu Coder: What CPython’s Official RISC-V Support Actually Guarantees
- ByteIota: RISC-V CPython Tier 3 — First Open ISA in Python’s Lineup