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AIMORELOGY Ovis: CVITEK CV1842H-P Pairs Arm A53 With a RISC-V C906 at 800 MHz for Edge Vision

2026-09-21 4 min read EN
RISC-V C906 CVITEK CV1842H-P edge AI NPU AI-ISP night vision embedded vision crowdfunding

Table of Contents

Published: 2026-09-21 · Category: RISC-V AI · Reading time: ~4 min · Status: DRAFT

What was announced

Covered by CNX Software on 16 September 2026, the AIMORELOGY Ovis is an open-source AI vision camera module built around the CVITEK CV1842H-P SoC. The pitch is full-colour 1080p night vision plus 1.5 TOPS of edge AI inference in a compact modular stack.

Target applications given are drones, robotics, security systems, smart cameras and custom embedded vision products.

Be clear about one thing up front: this is a crowdfunding announcement, not a product shipping to distribution.

The numbers, as published

ItemValue
SoCCVITEK CV1842H-P
Application CPU1× Arm Cortex-A53 @ 1.1 GHz
Companion CPU1× RISC-V C906 @ 800 MHz
NPU1.5 TOPS @ INT8, with BF16 support
ISPAI-ISP, real-time 1080p
Core board20 × 20 mm
On-board storage2 Gbit NAND flash
Core board I/OUSB, UART debug pads
Image sensorSC235HAI (on Sensor board)
Sensor board I/OEthernet, UART
OptionalCVBS board between Sensor and Core boards

Why the C906 is the interesting line

The Cortex-A53 at 1.1 GHz is unremarkable. The RISC-V C906 at 800 MHz is the datapoint worth tracking.

The C906 is one of the most widely deployed 64-bit RISC-V application cores in shipping silicon, and its appearance here is as a companion core in a vision SoC rather than as the headline processor. That is the current reality of RISC-V in edge AI silicon: the vector/control work sits on an open-ISA core while the matrix throughput lives in a proprietary NPU.

For engineers, the practical consequence is that your toolchain story splits in two. Anything you write for the C906 is standard RISC-V — GCC or LLVM, upstream debugger support, no architecture licence. The NPU is vendor-coupled regardless of which core you compile for. Choosing an open-ISA companion core does not by itself buy you NPU portability.

The mechanical design is the actual differentiator

The stacked three-board arrangement is more interesting than the spec sheet:

  1. Ovis Core board — 20 × 20 mm, SoC, 2 Gbit NAND, USB, UART debug pads
  2. Sensor board — SC235HAI sensor, adds Ethernet and UART
  3. Optional CVBS board — sits between the two for legacy analogue output

A 20 × 20 mm compute-and-NPU core with a separable sensor board means the same vision pipeline can be re-pointed at a different sensor without respinning the compute carrier. For anyone integrating vision into a gimbal, an inspection head or a robot body, that decoupling is the whole value proposition.

The AI-ISP claim — real-time 1080p with full-colour night vision — is the part to validate on real footage before committing. ISP quality claims are notoriously hard to assess from written specifications, and "full-colour night vision" spans a wide quality range.

How 1.5 TOPS frames the use case

1.5 TOPS at INT8 places this firmly in inference-at-the-sensor territory: classification, detection of a small number of object classes, presence/absence, simple tracking. It is not a platform for on-device transformer inference.

That is not a criticism — it is a sizing statement. The relevant question for a design is whether 1.5 TOPS at the sensor eliminates a round trip to a host, and for detection-class workloads it generally does. BF16 support is listed, which gives some headroom for models that do not quantise cleanly to INT8.

Not disclosed

The coverage leaves out most of what a design-in decision needs:

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com