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RISC-V Development

Fedora 45 RISC-V Rebuild: GCC Internal Compiler Errors on SpacemiT K1 and K3 Boards

RISC-V Fedora GCC glibc RVV SpacemiT-K1 SpacemiT-K3

Published: 2026-09-14 · Category: RISC-V Development · Reading time: ~4 min · Status: DRAFT

The rebuild is on track — the hardware is not entirely

The Fedora RISC-V group reports it is on target to release the Fedora 45 rebuild alongside the primary architecture images, maintaining sync parity with upstream. For anyone who remembers when riscv64 images lagged x86 by weeks, that parity is itself the headline.

The complications are in the hardware layer. Discussion at the group's 1 September 2026 meeting flagged ongoing stability problems: GCC internal compiler errors (ICEs) on SpacemiT K1 and K3 boards, which the group considers likely to be linked to new glibc vector optimisations interacting with kernel and OpenSBI limits. LLVM last-mile integration work is reported as progressing.

That single sentence deserves attention from anyone running Fedora on K1 or K3 hardware, because it points at a specific and repeatable class of failure.

Why glibc vector optimisations break compilers on real boards

An internal compiler error is not a normal build failure. It means GCC crashed while compiling valid input — a compiler bug, not a source bug. When a distribution rebuild starts hitting ICEs on one specific board family, the usual shape of the problem is a three-way interaction:

  1. glibc ships newly vectorised routines — string and memory functions with RVV 1.0 paths, enabled because the build target advertises vector support.
  2. The compiler generates code for a vector length or extension set that the hardware, or the platform firmware, does not fully implement or advertise consistently.
  3. The kernel or OpenSBI layer constrains what is actually reachable — for example via trap handling for vector context, or via riscv_v_vstate management — so the mismatch surfaces at runtime or during codegen rather than at configure time.

The Fedora group's wording is a hypothesis, not a root-cause confirmation. It says "likely linked to". Nobody has published a bisect, a failing test case, or a GCC bug ID in the material available. Treat it as a well-informed working theory from the people doing the rebuild, and nothing more.

What this means if you run Fedora on a K1 or K3

Practically:

What Fedora 45 actually brings

The second beta compose, Fedora-45-20260903.2, was built on 3 September 2026 after a beta freeze that began around 25 August. The version bumps are substantial across the board:

ComponentFedora 45
GCC16.2
glibc2.44
LLVM23
Python3.15
Binutils2.47
RPM6.1

Fedora 45 Beta is targeted for late September or early October. Release Engineering has an open ISO size check failure — several boot images exceed the maximum allowed size — and the blocker tracker lists six open bugs, including a kmscon regression affecting ARM minimal installs. Only the toolchain versions are relevant to the RISC-V question, but a GCC 16.2 plus glibc 2.44 combination is exactly the kind of jump that exposes latent vector-codegen issues.

Also noted: SiFive Big Sky in community hands

The same report notes that SiFive announced the 32-core P870-D "Big Sky" development server, with pricing and shipping dates still unannounced. Preliminary remote testing by community members indicates it is a capable platform for future RISC-V datacenter and build-farm use. "Preliminary remote testing" is early-adopter signal, not a benchmark — no numbers were published.

A 32-core RVA23-class machine in community hands is worth watching for exactly this reason: distribution rebuilds are currently bottlenecked on developer-accessible hardware, and more of it directly shortens the feedback loop on bugs like the K1/K3 ICEs.

Engineering takeaway

If you are evaluating RISC-V boards for a build farm or CI, this is the realistic picture in September 2026: distribution support has reached parity in release timing, but platform-specific toolchain bugs are still being discovered at rebuild time on shipping hardware. Budget for it. Keep a known-good toolchain snapshot, and follow the architecture list rather than assuming the bug is yours.


Sources

Verification notes