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RISC-V MCU

Infineon Says Its Next-Generation Automotive MCU Family Goes All-In on RISC-V

RISC-V Infineon AURIX TriCore TRAVEO T2G automotive MCU AUTOSAR Zephyr functional safety DRIVECORE

Published: 2026-09-18 · Category: RISC-V MCU · Reading time: ~5 min · Status: DRAFT

The statement and where it was made

At the 6th Smart Vehicle Chip Ecosystem Conference on 16 September 2026, Infineon's Liu Lin (Senior Manager, Automotive Marketing; RISC-V ecosystem lead for Greater China) stated that Infineon's next-generation automotive MCU products will use the RISC-V architecture across the board — quoted as going "all in" on RISC-V.

The claim is being carried by Chinese automotive trade press (Gasgoo, ifeng Auto, Autohome) that all reproduce the same talk. No equivalent English-language Infineon press release was found; treat this as a conference statement reported by trade media, not a product announcement with a datasheet behind it.

Today's portfolio is two architectures; the next one is one

Infineon's current MCU line-up is explicitly split:

SegmentFamilyCoreApplications cited
Low / mid-endTRAVEO T2GArmBody control, HMI
Mid / high-endAURIX (TC2 / TC3 / TC4)TriCore (in-house)Domain controllers, powertrain, BMS

The next generation consolidates both onto RISC-V. That is the part worth pausing on: this is not a RISC-V variant added beside an incumbent architecture, it is a consolidation of two existing architectures into one, including the replacement of Infineon's own proprietary TriCore ISA at the high end where functional-safety requirements are heaviest.

Scale context given in the same talk: Infineon's automotive electronics business was 50% of FY2025 revenue, Greater China is 38% of global business, MCU share moved from 32.1% (2025) to 36%, and per TechInsights (April 2026) Infineon has been the largest automotive semiconductor supplier since 2019.

The four stated reasons

Liu gave four rationales, and they are the ones a procurement or architecture team should interrogate:

  1. Flexibility — one unified architecture covering low-end through high-end.
  2. Open standard — no dependency on a single IP supplier.
  3. Modularity / extensibility — faster iteration.
  4. Ecosystem — existing collaborative work.

Reason 2 is the one with real weight for a Tier-1 doing multi-decade platform planning: an open ISA with multiple independent core suppliers is a multi-source supply argument, not an ideology argument. It is also the same reason a supplier can commit to long-term availability without a single licensor's roadmap constraining it.

Toolchain and OS work already done

The useful content in the talk is the ecosystem checklist, because it is concrete and dated:

For an engineering team, the March 2026 virtual prototype is the actionable item: it means architecture evaluation can start before silicon exists.

Standardisation

Two standardisation threads were cited:

Note the regional split: Infineon is simultaneously inside RVI's AUTO-SIG work internationally and the CACC group in China. Fragmentation between those two tracks remains an open risk for anyone shipping globally.

What is not disclosed

This is a strategy statement, not a product launch. The following are absent from all coverage found and must not be inferred:

Anyone quoting "Infineon is moving to RISC-V" without these caveats is overstating what was said.

Engineering takeaway

The signal is direction and commitment, not specifications. A supplier with roughly a third of the automotive MCU market saying its next generation is single-architecture RISC-V is meaningful for long-horizon platform planning — particularly for teams who care about multi-source availability and not being locked to one IP licensor.

The practical next step is the DRIVECORE RISC-V virtual prototype. Everything else — safety level, timing, performance, migration — is still unanswered, and until a numbered part with a safety manual exists, this should be treated as roadmap intelligence rather than a selection input.


Sources

Verification notes