Infineon Maps RISC-V for Automotive Zone Controllers at Hot Chips 2026 — MCU Island + MPU Island, AUTO-SIG Profiles, and the Three-Architecture AURIX Portfolio

At Hot Chips 2026, Infineon laid out its automotive RISC-V architecture direction in one of the most consequential talks of the conference for the open-ISA ecosystem. The message was deliberately pragmatic: RISC-V is not replacing TriCore or Arm in Infineon’s lineup — it is joining them as a third CPU architecture under the AURIX brand, aimed at the industry’s transition from domain controllers to zonal control units and, eventually, the central vehicle computer. Just as important was the warning: the ISA is the easy part. Automotive-qualified toolchains, SoC architecture, and functional-safety enablement will decide how fast RISC-V actually lands in cars.

This article consolidates the technical substance of the talk from multiple independent reports of the presentation. Note that Infineon presented an architecture direction, not a specific shipping chip — no part numbers, process nodes, or availability dates were announced.

From Domain Controllers to Zonal Architecture

Infineon framed the automotive E/E (electrical/electronic) architecture transition in three stages. Each stage redistributes compute and rewires the vehicle:

The real prize is the wiring harness — one of the heaviest, most expensive, and most labor-intensive subsystems in a modern vehicle. Consolidating body and comfort functions into zones that share wiring cuts harness length and weight, moves power distribution closer to the loads, and reduces assembly complexity. The harness decision therefore affects the vehicle far beyond the electronics bill of materials.

The Zonal Workload Problem: Orders-of-Magnitude Timing Spread

Why can’t one homogeneous processor serve a zone controller? Because the workloads that land on it differ by orders of magnitude in timing:

A single zonal device may combine deterministic real-time control, digital signal processing, AI inference, audio processing, low-power service functions, and communication processing — on one automotive-qualified part, while a background task must never disturb a safety-critical control loop. That is a heterogeneous-workload problem, and it is the core argument for a multi-architecture, multi-island silicon design.

Two Paths to a Zone Controller — Infineon Picks Path A

Infineon contrasted two broad approaches to zonal controller design:

The reasoning: keeping local, tactical, latency-sensitive control inside the zone while sending global strategy upstream shrinks the vehicle’s attack surface (fewer network paths expose vehicle functions), simplifies maintenance (functions can be isolated within a zone), and cuts system cost by eliminating endpoint ECUs and decentralizing power distribution.

MCU Island + MPU Island: Heterogeneous Super-Integration

For higher-end “super-integration” zone controllers, Infineon proposes combining two compute islands on one automotive-qualified device:

• MCU island — deterministic, safety-critical work: fast control loops, lock-step execution, hard real-time guarantees.
• MPU island — non-real-time workloads on a POSIX-compatible adaptive software stack (think Adaptive AUTOSAR), richer applications, and faster boot/wake behavior than a full application SoC.

This split gives software teams a place to run compute-heavy or convenience functions without forcing them onto the real-time core, and lets a zone scale from L2 toward L2+ and L3 autonomy. The architecture must also scale down: a sensor-adjacent zone needs DSP and AI acceleration, while a body-control zone needs modest compute, many I/O channels, and low standby power. Both benefit from common software interfaces and tools — they do not need the same core count, memory, or accelerator mix.

Why RISC-V — the Pragmatic Case

Infineon’s argument for RISC-V was business- and engineering-driven, not ideological:

• No IP-level lock-in for 15-year lifecycles. Automotive silicon is qualified for roughly 15 years of production. A single open, scalable ISA reduces dependence on any one processor IP supplier across that horizon.
• One ISA across domains. The same open ISA spans automotive, industrial, and IoT, easing knowledge sharing and creating ecosystem synergies across product lines.
• Multi-vendor sourcing. An open ISA supports designs from multiple vendors — a sourcing-strategy lever for a company that ships hundreds of millions of MCUs annually.
• Microarchitectural freedom. The ISA specifies what, not how. Instruction latency, cache structure, memory hierarchy, coherency method, interconnect, lock-step cores, error tracking, and security blocks all remain silicon-designer choices — exactly where automotive differentiation happens.

Three Architectures, One Portfolio: TriCore + Arm + RISC-V

Infineon does not view RISC-V as a replacement. The company is building a three-architecture automotive portfolio: the established TriCore architecture (the AURIX workhorse for powertrain and chassis), Arm-based products, and a new RISC-V line under the AURIX brand. This mirrors the broader reality of automotive computing: the ISA is only one layer of the problem. Functional safety, cybersecurity, virtualization, deterministic real-time execution, software tooling, standardized interfaces, long-term support, and ecosystem compatibility must all be solved regardless of instruction set.

RVI AUTO-SIG Profiles and the RVM Virtualization Requirement

Standardization, Infineon argued, should happen through RISC-V International’s AUTO-SIG profiles that match industry requirements. Two structural points from the talk:

Virtualization also becomes the mechanism for assigning safety-related workloads, service software, and application workloads to controlled environments while preserving boundaries between them.

Power: A Cross-Cutting Design Constraint, Not a Slide Number

Infineon deliberately did not present a single power-consumption figure for a future RISC-V automotive product. Instead, power was framed as a constraint that reaches across the processor core, memory system, connectivity, accelerators, and the software stack. A controller that meets performance targets but wastes energy raises thermal demands and erodes the value of zone consolidation.

The Toolchain Is the Product

The sharpest takeaway for engineering teams: RISC-V removes the licensing tax and grants microarchitectural freedom — but you are also on the hook for qualifying your own toolchain, your own functional-safety artifacts, and your own security-certification evidence. That is a massive operational burden unless the ecosystem matures fast. This is precisely where RISC-V International’s AUTO-SIG work, certification programs, and the growing list of automotive-grade RISC-V parts (Nuclei NA900 at ASIL-D, Guoxin Tech’s automotive chip standard, Quintauris RT-Europa) plug in.

What This Means for the RISC-V Ecosystem

• A top-three automotive MCU vendor is now designing with RISC-V. Infineon joins NXP, Renesas, and Qualcomm in publicly committing to RISC-V in automotive silicon — the “will it happen” phase is over; the “how fast” phase has begun.
• Profiles over persuasion. The AUTO-SIG profile route (RV32E+I+M+U baseline, optional FP/V/H) signals that automotive adoption will be standardized through requirements documents, not marketing.
• Virtualization is table stakes. Mixed-criticality hosting via RVM is now a stated hard requirement — RISC-V hypervisor implementations matter for automotive as much as for servers.
• Toolchains are the bottleneck. Qualified compilers, safety cases, and certification evidence remain the rate limiter — an opportunity for tool vendors and an obligation for silicon vendors.
• Zone controllers favor heterogeneity. MCU island + MPU island designs play to RISC-V’s strength: one ISA, many microarchitectures, tuned per island.

For RISC-V MCU and IP vendors watching this space: the requirements list above — AUTO-SIG profile compliance, RVM virtualization, lock-step and error-tracking capabilities, qualified toolchains — is effectively the checklist for entering the automotive zonal-controller market.