Linux 7.3 was released by Linus Torvalds on October 18, 2026, and the merge window for 7.4 opened the following day. For RISC-V this was one of the densest cycles in recent memory: eleven ISA extensions gained initial definitions and discovery, the MMU cache-range path learned to use ASIDs and Svinval, QoS tagging arrived in the context switcher, and the board tree grew by a 64-bit AI SoC, a pair of Milk-V boards and a fistful of peripheral nodes for the incumbent vendors.
What follows is a technical walk through the RISC-V portion of the release, grouped by what it actually changes for people shipping RISC-V hardware.
Provenance: the extension list, the MMU and QoS items and the SoC/board entries below are taken from the Linux 7.3 release summary published by CNX Software on 2026-10-20, which reproduces the architecture pull request around Linus's 2026-10-18 Linux 7.3 announcement. Anything we compute ourselves is marked as an estimate.
The headline for anyone bringing up a new core is the arrival of Smcdeleg and Smcntrpmf as recognized extensions, together with Smcsrind and Sscsrind for indirect CSR access, and Ssccfg for counter configuration.
Historically, RISC-V fixed mcycle and minstret in the privileged spec and left it to each implementation to decide which events could hang off mhpmcounter. The practical consequence was that perf on a RISC-V board typically exposed cycles and instructions and little else that could be trusted across vendors. Delegation changes the mechanics: with Smcdeleg, a hypervisor or kernel can hand counter access down so that reading a hardware counter does not require an M-mode trap each time.
The Linux kernel began accepting RISC-V PMU drivers in 6.2 and had only a handful of vendor PMUs by 6.8. Extension discovery for the delegation family is the prerequisite for the next step — a generic, non-vendor PMU path.
Practical read: if you are validating a new RISC-V core, do not assume perf stat will give you cache and branch numbers just because the counters exist in RTL. The chain has three links and all three must be closed: the core must implement the counters, the firmware must open the access path, and the kernel must know which events the core can count.
Ssqosid — the supervisor-level extension for QoS ID tagging — received initial CPU context switch support. On cores that implement it, a software thread can be tagged so that shared caches and memory controllers can apply capacity allocation, way-masking or bandwidth policies per workload class instead of per core.
This is the mechanism a server SoC needs before "this LLM prefill job must not evict the latency-critical database working set from L3" becomes an enforceable policy rather than a wish. It also pairs naturally with the Za64rs reservation-set definition that landed in the same cycle, which bounds the granule on which atomics can claim exclusive access.
update_mmu_cache_range(): flush by ASID, and Svinval where availableTwo changes here matter more for throughput than their commit titles suggest. The RISC-V implementation of update_mmu_cache_range() now uses flush-by-ASID, so a TLB maintenance operation does not have to nuke entries belonging to unrelated address spaces, and it takes advantage of Svinval on microarchitectures that implement it, which allows fine-grained invalidations instead of a full sfence.vma every time.
The other changes in the same area are worth noting because they are the ones that bite in production:
Zacas and Zabha instruction use is now controlled by assembler directives rather than -march flags that affected the whole kernel image — the same approach arm64 took, and the right one: it lets a single kernel contain instruction sequences that are patched in only on cores that support them.vDSO section offsets are extracted at build time instead of at run time, removing boot-time work.do_trap_break().CONFIG_CMA_SIZE_PERNUMA is enabled.Two items make RISC-V systems behave more like x86/arm64 servers:
ARCH_HAS_ACPI_TABLE_UPGRADE is enabled for RISC-V (with a missing include fixed in the ACPI code), which allows boot-time ACPI table override methods that already exist on arm64 and x86 — a debugging feature more than a production one, but a sign the ACPI boot path is being treated as first-class.arch_get_idle_state_flags(). Idle residency accounting on ACPI RISC-V platforms has been a recurring papercut; this is the fix.Three SoC families gained or expanded upstream support in 7.3:
| SoC | Vendor / type | What landed |
|---|---|---|
| K230 | Canaan / Kendryte, 64-bit RISC-V AI SoC (successor to K210) | Initial SoC support, plus initial board support for CanMV-K230 and K230-EVB |
| SG2000 / SG2002 | Sophgo, hybrid Arm + RISC-V SoC | RISC-V side support added (previously only reachable via the Arm cores), plus initial support for Milk-V Duo S (SG2000) and Duo 256M (SG2002); DMA mux can now set controller channel numbers |
| SpacemiT K3 / K1 | SpacemiT, RVA23 AI CPU family | K3: SD card, QSPI, SPI controller, USB + PHY, I2S node, ETH PHY reset-delay and PHY-ID fixes. K1: cpufreq enablement, max core voltage fix, symbolic PDAM IDs |
| StarFive JHB100 | StarFive, server-class | SPI flash controller (SFC) support, PLIC devicetree bindings, PCIe controller resource-leak and runtime-PM fixes |
| TH1520 | Alibaba T-Head | th1520-dw-hdmi: fixed error checking on dw_hdmi_probe() return value and fixed the remove() callback; remaining IO-expander DT changes for LicheePi 4a |
Two of these deserve a second look. The K230 entry is the first upstream Linux support for Canaan's 64-bit RISC-V AI SoC generation, which has been shipping in vision boards but has lived on vendor BSPs. And SG2000 RISC-V support is more significant than it reads: the chip already worked when booted through its Arm cores, so the new code means the RISC-V cores can now run Linux as the main application processor on the same silicon — relevant for anyone building a dual-ISA product where BOM pressure points at the cheaper core cluster.
The SpacemiT entries are incremental but land in the right places. K3 gained SPI, USB and I2S nodes plus Ethernet PHY fixes, which is what a board needs before audio and storage peripherals stop being out-of-tree patches. Board-level additions in the same release cover Milk-V Jupiter (CPU DVFS on K1), Banana Pi BPI-CM6 and its IO board, Orange Pi R2S (PCIe), plus the K3 Pico-ITX and CoM260 (EEPROM, NOR flash, RTL8211F PHY tuning).
A kernel merge is evidence that code exists and survives review; it is not a performance claim. Three statements are worth keeping separate:
perf will report anything beyond cycles and instructions on your core.If you are shipping a RISC-V board: the actionable item is to diff your out-of-tree device tree against the 7.3 upstream nodes for K1, K3, TH1520, SG2000 and JHB100, and drop whatever is now duplicated. Every node you delete is one less thing to rebase on the next kernel bump.
Documentation/devicetree/bindings/riscv/extensions.yaml2026 年 10 月 18 日，Linus 发布 Linux 7.3，7.4 的合并窗口次日开启。对 RISC-V 来说，这是近年来最密的一个周期之一：11 个 ISA 扩展拿到初始定义与探测支持，MMU 的 range-flush 路径学会用 ASID 和 Svinval，QoS 标记落地到上下文切换，板级树则新增一颗 64 位 AI SoC、两块 Milk-V 开发板，以及若干既有厂商的外设节点。
下面按“对实际做 RISC-V 硬件的人意味着什么”来拆解 RISC-V 相关的改动。
来源说明：扩展清单、MMU 与 QoS 条目、以及 SoC/板级条目，均取自 CNX Software 2026-10-20 发布的 Linux 7.3 发布摘要，该文对应 Linus 在 2026-10-18 的 Linux 7.3 公告。任何我们自行计算的内容都会标注为推算。
对做新核的人来说，最重要的条目是 Smcdeleg 与 Smcntrpmf 被正式识别，同时 Smcsrind、Sscsrind（间接 CSR 访问）和 Ssccfg（计数器配置）一并纳入。
历史上，RISC-V 特权规范把 mcycle 和 minstret 定死，mhpmcounter 能挂哪些事件则交给实现方自定。结果是 RISC-V 平台上跑 perf，长期停在“cycles 和 instructions 可用，其余看运气”。委托机制改变了这一点：有了 Smcdeleg，Hypervisor 或内核可以把计数器访问权限下放，读性能计数器不再每次都陷入 M 模式。
内核从 6.2 才接受第一个 RISC-V PMU 驱动，到 6.8 也只覆盖少数厂商。而委托类扩展的探测支持，正是走向通用（非厂商专用）PMU 路径的前置条件。
实操提醒：如果你在验证一颗新核，不要因为 RTL 里计数器存在就假设 perf stat 能给出 cache/branch 数据。这条链有三环，缺一不可：核里真有计数器、固件打开访问路径、内核知道这颗核能测哪些事件。
Ssqosid（QoS ID 标记的 S 模式扩展）拿到了初始的 CPU 上下文切换支持。在实现了该扩展的核上，软件线程可以被打上 QoS 标签，让共享缓存与内存控制器按工作负载等级（而不是按核）执行容量分配、way-masking 或带宽策略。
这正是服务器 SoC 在把“这个 LLM prefill 任务不能把延迟敏感的数据库工作集挤出 L3”从愿望变成可执行策略之前所需要的机制。它在逻辑上与同周期落地的 Za64rs（预约集粒度定义）相配，后者界定了原子操作争抢独占访问的粒度。
update_mmu_cache_range()：按 ASID flush，有 Svinval 就用这里两处改动对吞吐的意义比提交标题大：update_mmu_cache_range() 的 RISC-V 实现改用 flush-by-ASID，TLB 维护不必再连带清掉无关地址空间的表项；在实现了 Svinval 的微架构上则利用它做细粒度失效，而不是每次全量 sfence.vma。
同一区域里还有几条“生产环境会咬人”的修复值得记下：
Zacas/Zabha 指令的使用改由汇编器指示符控制，不再用会影响整个内核镜像的 -march 编译选项 — 与 arm64 同一做法，也是正确做法：同一份内核可以含有只在支持的核上被 patch 进来的指令序列。vDSO 段偏移改为构建期提取，去掉启动期开销。do_trap_break() 的路径。CONFIG_CMA_SIZE_PERNUMA 时分配正确的全局与 per-node 内存池。ARCH_HAS_ACPI_TABLE_UPGRADE（并修了 ACPI 代码中缺失的 include），使 arm64/x86 早已具备的启动期 ACPI 表覆盖手段可用 — 更像调试能力，但说明 ACPI 启动路径已被当作一等公民对待。arch_get_idle_state_flags()。ACPI RISC-V 平台的 idle 驻留统计一直是个反复的小痛点。| SoC | 厂商 / 类型 | 本次落地内容 |
|---|---|---|
| K230 | 嘉楠 Canaan / Kendryte，64 位 RISC-V AI SoC（K210 后继） | SoC 初始支持，以及 CanMV-K230 与 K230-EVB 初始板级支持 |
| SG2000 / SG2002 | 算能 Sophgo，Arm + RISC-V 混合 SoC | 新增 RISC-V 侧支持（此前只能经 Arm 核启动），并初始支持 Milk-V Duo S（SG2000）与 Duo 256M（SG2002）；DMA mux 可为控制器设置通道号 |
| SpacemiT K3 / K1 | 进迭时空，RVA23 AI CPU 系列 | K3：SD 卡、QSPI、SPI 控制器、USB 与 PHY、I2S 节点、ETH PHY reset delay 与 PHY ID 修复。K1：启用 cpufreq、修复 CPU 核心最大电压、符号化 PDAM ID |
| StarFive JHB100 | 赛昉，服务器级 | SPI Flash 控制器（SFC）支持、PLIC devicetree binding、PCIe 控制器资源泄漏与 runtime PM 顺序修复 |
| TH1520 | 阿里平头哥 | th1520-dw-hdmi：修复 dw_hdmi_probe() 返回值的错误检查与 remove() 回调；LicheePi 4a 剩余 IO 扩展芯片 DT 调整 |
其中两条值得多看一眼。K230 是嘉楠 64 位 RISC-V AI SoC 首次进入上游内核 — 这颗芯片此前在视觉板卡上出货，但一直活在厂商 BSP 里。SG2000 的 RISC-V 支持意义比字面更大：该芯片经由 Arm 核启动时本来就能跑，新代码意味着同一颗硅片上 RISC-V 核现在可以充当主应用处理器 — 对做双 ISA 产品、BOM 压力指向更便宜核簇的团队直接相关。
进迭时空的条目增量但落点正确：K3 补上了 SPI、USB、I2S 节点与以太网 PHY 修复，这正是板子要跑通音频与存储外设之前所缺的。同版本的板级新增覆盖 Milk-V Jupiter（K1 上 CPU DVFS）、香蕉派 BPI-CM6 及其 IO 板、香橙派 R2S（PCIe），以及 K3 Pico-ITX 与 CoM260（EEPROM、NOR flash、RTL8211F PHY 调参）。
内核合并只说明代码存在且通过了社区审查，不是性能结论。三件事要分开看：
perf 在你的核上是否只有 cycles/instructions。如果你在出货 RISC-V 板子：可立即执行的动作是把自己的 out-of-tree 设备树与 7.3 上游的 K1、K3、TH1520、SG2000、JHB100 节点做一次 diff，删掉所有已经重复的部分。每删一个节点，下一次内核升级就少一次 rebase。
Documentation/devicetree/bindings/riscv/extensions.yamlЯдро Linux 7.3 выпущено 18 октября 2026 года. Для RISC-V это один из самых насыщенных циклов: расширения Smcdeleg, Smcntrpmf, Smcsrind, Sscsrind и Ssccfg (делегирование счётчиков производительности), Ssqosid (теги QoS в переключении контекста), а также Za64rs, Zicclsm, Ziccamoa, Ziccif, Ziccrse получили начальное определение и обнаружение.
В update_mmu_cache_range() теперь используется flush-by-ASID и Svinval там, где он реализован. Включён ARCH_HAS_ACPI_TABLE_UPGRADE; при наличии UEFI runtime services ядро использует их для перезагрузки и выключения; исправлено переключение broadcast timer в состояниях ACPI LPI.
Новые SoC и платы: K230 (Canaan, 64-бит AI SoC) с CanMV-K230 и K230-EVB; SG2000/SG2002 (Sophgo) теперь с поддержкой RISC-V-стороны и платами Milk-V Duo S / Duo 256M; SpacemiT K3 (SPI, USB, I2S, Ethernet PHY) и K1 (cpufreq); StarFive JHB100 (SFC, PLIC) и исправления PCIe; TH1520 — th1520-dw-hdmi.
Важное ограничение: слияние в ядро подтверждает наличие кода, а не производительность. Список событий PMU по-прежнему должен предоставить вендор.
منابع: LKML, 2026-10-18 · CNX Software, 2026-10-20
Linux 7.3 se publicó el 18 de octubre de 2026. Es uno de los ciclos más densos para RISC-V: las extensiones Smcdeleg, Smcntrpmf, Smcsrind, Sscsrind y Ssccfg (delegación de contadores de rendimiento), Ssqosid (etiquetado QoS en el cambio de contexto) y Za64rs, Zicclsm, Ziccamoa, Ziccif, Ziccrse obtuvieron definición y descubrimiento iniciales.
update_mmu_cache_range() ahora usa flush-by-ASID y aprovecha Svinval donde está implementado. Se habilita ARCH_HAS_ACPI_TABLE_UPGRADE; con UEFI runtime services disponibles el núcleo los usa para reiniciar y apagar; se corrige el cambio de timer de broadcast en estados ACPI LPI.
Nuevos SoC y placas: K230 (Canaan, SoC AI de 64 bits) con CanMV-K230 y K230-EVB; SG2000/SG2002 (Sophgo) ahora con soporte del lado RISC-V y placas Milk-V Duo S / Duo 256M; SpacemiT K3 (SPI, USB, I2S, PHY Ethernet) y K1 (cpufreq); StarFive JHB100 (SFC, PLIC) y correcciones PCIe; TH1520 — th1520-dw-hdmi.
Límite importante: un merge demuestra que el código existe, no que sea más rápido. La lista de eventos del PMU sigue siendo responsabilidad del fabricante.
Fuentes: LKML, 2026-10-18 · CNX Software, 2026-10-20
Linux 7.3 est sorti le 18 octobre 2026. C'est l'un des cycles les plus denses pour RISC-V : les extensions Smcdeleg, Smcntrpmf, Smcsrind, Sscsrind et Ssccfg (délégation des compteurs de performance), Ssqosid (étiquetage QoS dans le changement de contexte) ainsi que Za64rs, Zicclsm, Ziccamoa, Ziccif, Ziccrse ont reçu une définition et une détection initiales.
update_mmu_cache_range() utilise désormais flush-by-ASID et tire parti de Svinval là où il est implémenté. ARCH_HAS_ACPI_TABLE_UPGRADE est activé ; si les services d'exécution UEFI sont disponibles, le noyau les utilise pour redémarrer et éteindre ; le basculement du broadcast timer dans les états ACPI LPI est corrigé.
Nouveaux SoC et cartes : K230 (Canaan, SoC IA 64 bits) avec CanMV-K230 et K230-EVB ; SG2000/SG2002 (Sophgo) avec support côté RISC-V et cartes Milk-V Duo S / Duo 256M ; SpacemiT K3 (SPI, USB, I2S, PHY Ethernet) et K1 (cpufreq) ; StarFive JHB100 (SFC, PLIC) et correctifs PCIe ; TH1520 — th1520-dw-hdmi.
Limite importante : un merge prouve que le code existe, pas qu'il soit plus rapide. La liste d'événements du PMU reste à la charge du fabricant.
Sources : LKML, 2026-10-18 · CNX Software, 2026-10-20
Linux 7.3 wurde am 18. Oktober 2026 veröffentlicht. Für RISC-V ist es einer der dichtesten Zyklen: Die Erweiterungen Smcdeleg, Smcntrpmf, Smcsrind, Sscsrind und Ssccfg (Delegation von Performance-Zählern), Ssqosid (QoS-Tagging im Context-Switch) sowie Za64rs, Zicclsm, Ziccamoa, Ziccif, Ziccrse erhalten erste Definition und Discovery.
update_mmu_cache_range() nutzt jetzt flush-by-ASID und Svinval, wo implementiert. ARCH_HAS_ACPI_TABLE_UPGRADE ist aktiv; mit UEFI-Runtime-Services nutzt der Kernel diese zum Neustart und Ausschalten; der Broadcast-Timer-Wechsel in ACPI-LPI-Zuständen ist gefixt.
Neue SoCs und Boards: K230 (Canaan, 64-Bit-KI-SoC) mit CanMV-K230 und K230-EVB; SG2000/SG2002 (Sophgo) nun mit RISC-V-Unterstützung und Milk-V Duo S / Duo 256M; SpacemiT K3 (SPI, USB, I2S, Ethernet-PHY) und K1 (cpufreq); StarFive JHB100 (SFC, PLIC) plus PCIe-Fixes; TH1520 — th1520-dw-hdmi.
Wichtige Grenze: Ein Merge belegt, dass Code existiert, nicht dass er schneller ist. Die PMU-Eventliste muss weiterhin der Hersteller liefern.
Quellen: LKML, 2026-10-18 · CNX Software, 2026-10-20
هسته لینوکس ۷٫۳ در ۱۸ اکتبر ۲۰۲۶ منتشر شد. برای RISC-V یکی از پرترافیکترین چرخههای اخیر است: افزونههای Smcdeleg، Smcntrpmf، Smcsrind، Sscsrind و Ssccfg (واگذاری شمارندههای کارایی)، Ssqosid (برچسب QoS در تعویض زمینه) و همچنین Za64rs، Zicclsm، Ziccamoa، Ziccif، Ziccrse تعریف و شناسایی اولیه گرفتند.
update_mmu_cache_range() اکنون از flush-by-ASID و در صورت پشتیبانی از Svinval استفاده میکند. ARCH_HAS_ACPI_TABLE_UPGRADE فعال شد؛ در صورت وجود UEFI runtime services هسته از آنها برای ریاستارت و خاموشکردن استفاده میکند؛ و جابهجایی broadcast timer در حالتهای ACPI LPI اصلاح شد.
SoCها و بردهای جدید: K230 (Canaan، SoC هوش مصنوعی ۶۴ بیتی) با CanMV-K230 و K230-EVB؛ SG2000/SG2002 (Sophgo) با پشتیبانی سمت RISC-V و بردهای Milk-V Duo S و Duo 256M؛ SpacemiT K3 (SPI، USB، I2S، PHY اترنت) و K1 (cpufreq)؛ StarFive JHB100 (SFC، PLIC) و اصلاحات PCIe؛ TH1520 — th1520-dw-hdmi.
یک محدودیت مهم: ادغام در هسته فقط وجود کد را ثابت میکند، نه سرعت را. فهرست رویدادهای PMU همچنان باید توسط سازنده ارائه شود.
منابع: LKML، ۲۰۲۶-۱۰-۱۸ · CNX Software، ۲۰۲۶-۱۰-۲۰