Micro Magic MagicV: A 5 GHz, 13,000 CoreMark 64-bit RISC-V Core Running Linux, Zephyr and FreeRTOS

Published: 2026-09-02 | Category: RISC-V Development | Reading time: ~5 min

On 31 August 2026, Sunnyvale-based Micro Magic, Inc. announced general availability of its MagicV family of 64-bit RISC-V processor cores, demonstrating a multi-core configuration running Linux, Zephyr, and FreeRTOS.

The label matters from the outset: every performance figure below is vendor-stated in the company's press release. No independent measurement, third-party benchmark, or published silicon has been offered alongside them. Read the numbers as a claim of record, not a verified result.

The performance claims, as stated

Micro Magic states:

• The fastest 64-bit RISC-V core reaches 5 GHz and 13,000 CoreMarks at 1.1 V
• A single core at 0.8 V delivers 11,000 CoreMarks at 4.25 GHz while consuming 200 mW
• Peak efficiency is 110,000 CoreMarks/Watt
• An ultra-low-power variant consumes 10 mW at 1 GHz, and under 500 mW at 5 GHz
• Cores ship in 1, 2, or 4-core configurations
• Each core includes a high-performance hardware FPU
• All figures are quoted for 16 nm, with more advanced nodes stated as available

If those numbers hold up on silicon, the interesting one is not 5 GHz — it is 11,000 CoreMarks at 200 mW. Roughly 55 CoreMarks per milliwatt per core would put 4-core server, automotive, and handset configurations inside a thermal envelope that most out-of-order 64-bit designs cannot reach without active cooling.

Why the operating voltage story matters more than the clock

The press release quotes two operating points: 1.1 V for maximum frequency, and 0.8 V for the efficiency point. That second number is the one with engineering consequence.

Dropping from 1.1 V to 0.8 V on the same core costs roughly 1,800 CoreMarks and 750 MHz, but takes power down to 200 mW. For anyone designing battery-powered or passively cooled equipment, that is the trade space that matters: a 64-bit core with hardware floating point that stays useful at 0.8 V means vector workloads and full Linux userspace become viable in form factors that previously had to drop to 32-bit microcontrollers.

Micro Magic also claims 10 mW at 1 GHz for the ultra-low-power core in the same family. A 1 GHz 64-bit core at 10 mW would compete directly with the power envelope of high-end 32-bit MCU subsystems, while retaining a flat 64-bit address space and an MMU-capable software stack.

Software: three operating systems, demonstrated on multicore

The announcement states that Linux, Zephyr, and FreeRTOS all run on MagicV processors, demonstrated in a multi-core configuration.

That combination is the practical minimum for a core intended to span the market list Micro Magic gives — automotive, cell phones, rack-mount servers, and watches. Linux covers the application and server end; Zephyr covers connected embedded and RTOS-class work; FreeRTOS covers the deeply embedded and certified-control end. Having all three demonstrated rather than merely planned is what determines whether an IP core is usable by product teams on a reasonable schedule.

Note what this implies architecturally but is not stated: running Linux requires an MMU, privilege modes, and a ratified profile. The release specifies none of them.

What is not disclosed

This is the longer list, and it is where a buyer's real risk sits:

• ISA — no statement on base extensions (M/A/F/D/C), RVV support or vector length, hypervisor extension, or a ratified profile such as RVA22 or RVA23
• Microarchitecture — no issue width, pipeline depth, in-order versus out-of-order, branch predictor, or cache hierarchy
• Memory system — no L1/L2 sizes, no interface width, no DDR generation, and no multicore coherency or interconnect mechanism for the 2-core and 4-core configurations
• Implementation — no die area, cell library, hard macro availability, or target foundry; no nodes named beyond "16 nm, with more advanced available"
• Toolchain — no GCC or LLVM support level stated, and no statement on whether the OS ports are mainline or vendor forks
• Commercial and validation — no licence model, royalty structure, or silicon availability date; no independent benchmark, no published silicon, and no measurement conditions (CoreMark compiler flags, memory system, temperature, or whether figures are simulated, emulated, or measured)

Taken together, these gaps mean MagicV should be treated as an early-availability IP announcement, not a characterised product.

Company context

Micro Magic describes itself as a private, self-funded company providing tools, services, and IP for the design of high-speed, low-power SoCs, and states it is actively exploring strategic partnerships or acquisitions with industry leaders. CEO Mark Santoro is quoted on customer reaction to the power figures; co-founder Lee Tavrow (Ph.D., MIT) on die area, cost, and low-voltage capability.

That last line is worth flagging for anyone considering MagicV for a multi-year programme. IP continuity is a material input to a silicon decision, and it is an open question here.

How to evaluate it

Questions to put to Micro Magic before any design commitment:

1. Is the 13,000 CoreMark figure measured on silicon, or simulated? Under what compiler and flags?
2. Is RVV 1.0 supported, at what vector length, and is it compiler-accessible today?
3. Is there a ratified profile target (RVA22 / RVA23), and a compliance statement?
4. Are the Linux, Zephyr and FreeRTOS ports mainline, or vendor forks? Are patches public?
5. What is the deliverable — RTL, hardened macro, or FPGA bitstream — at which foundries and nodes?
6. Is there a coherency story for the 2-core and 4-core configurations?

What it signals regardless

Whether or not the numbers hold, the direction is clear. Vendors are now competing on performance-per-watt of 64-bit RISC-V at both ends of the curve simultaneously — the 5 GHz ceiling and the 10 mW floor — within one core family. That is a different posture from the earlier phase of the ecosystem, where 64-bit RISC-V meant server-class parts and 32-bit meant microcontrollers, with a largely empty middle.

Sources

1. ACCESS Newswire — "Micro Magic, Inc. Announces Immediate Availability of the World's Fastest and Lowest Power 64-bit RISC-V Processors" (Sunnyvale, CA, 31 August 2026): https://www.accessnewswire.com/newsroom/en/computers-technology-and-internet/micro-magic-inc.-announces-immediate-availability-of-the-worlds-f-1213665
2. Micro Magic corporate site: https://www.micromagic.com

Verification notes

• All numbers in this draft are quoted from the vendor press release (source 1) and are labelled as vendor-stated throughout.
• No CoreMark.org submission, independent review, or silicon measurement was located for MagicV as of 2026-09-02. The "world's fastest" and "world's highest performance/power" claims are the vendor's own.
• The 55 CoreMarks/mW-per-core figure in this draft is arithmetic derived from the vendor's stated 11,000 CoreMarks at 200 mW. It is a derived figure, not a vendor claim.
• Do not add ISA, cache, process, or availability details — none have been published.