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NanoCore 3D-CIM: RISC-V Heterogeneous Compute-in-Memory Chips Near Mass Commercialization

2026-09-09 5 min read EN
RISC-V compute-in-memory CIM 3D-CIM edge AI LLM inference

Table of Contents

The funding

Hangzhou NanoCore Electronic Technology (杭州微纳核芯电子科技有限公司) announced on 9 September 2026 that it has closed a C1 round of ¥1 billion (approximately 10亿元). Financial investors included 优势资本, 元昊投资, 金浦投资, 阳光人寿, 元禾璞华, 德联资本, 宽桥恒松 and 厚雪资本; strategic and industrial participants included 美格智能 (MeiG Smart), 恒旭资本, 华勤技术 (Huaqin Technology) and an unnamed large-model company. Multiple existing shareholders followed on.

The company was founded in 2021, incubated at the Peking University Information Technology Institute in Zhejiang, and is headquartered in Xiaoshan District, Hangzhou. Its founder, chief scientist and chairman is Ye Le (叶乐), an associate professor in Peking University's School of Integrated Circuits, whose published work covers compute-in-memory AI chips, 3D integrated chips and AIoT silicon.

NanoCore has now raised roughly seven rounds. Cumulative B-series funding exceeded ¥1 billion by June 2026, so the company has taken in more than ¥2 billion in under twelve months. Its cap table includes Xiaomi, Lenovo Capital, GigaDevice (兆易创新), SMIC Capital, China Mobile's Chain-Lead Fund, Luxshare-ICT's investment arm, SDIC Venture Capital (深创投) and the China Internet Investment Fund.

What 3D-CIM actually means

NanoCore's pitch is a three-layer architecture it calls 3D-CIM™:

  1. DRAM 3D near-memory computing — stacking or closely coupling compute with DRAM to shorten the path between weights and execution units.
  2. SRAM compute-in-memory — embedding arithmetic directly in the SRAM array so matrix and tensor operations, which dominate transformer inference, complete in place.
  3. RISC-V heterogeneous compute-in-memory — a RISC-V-based heterogeneous layer handling the general-purpose and control work that pure CIM arrays do badly.

That third element is why this belongs on a RISC-V site. Compute-in-memory is very good at dense linear algebra and very bad at branching, scheduling and I/O. Pairing it with an open-standard RISC-V control plane is the pragmatic answer, and it lets the company use an ISA without per-core licensing cost on a part that is competing on die area.

The one number they do publish

NanoCore states that measured silicon shows its SRAM compute-in-memory delivers 4–6× the compute density and 5–10× the energy efficiency of a von Neumann architecture baseline.

Two caveats are important. First, "measured tapeout result" (实测流片结果) is the company's own characterisation — no baseline part is named, no workload is given, and no measurement methodology is published. Second, compute density and energy efficiency are ratios against an unnamed reference, not absolute capability. A 5× efficiency claim against a poorly chosen baseline is worth very little.

The company also says its LP-CIM™ series targets endpoint applications through close work with memory manufacturers, while its cloud-side parts aim to reach advanced-node-equivalent compute on a mature process node — a supply-chain argument rather than a performance one, and a relevant one for anyone thinking about long-term availability and multi-source procurement.

What is not disclosed

This is where the announcement is thinnest:

For a company claiming imminent mass commercialisation, the absence of any per-part datasheet is the single biggest gap.

Commercial status and target markets

NanoCore says it has completed development of the chip, the board/server form factors and the full software stack. It expects to run multi-scenario customer sampling within the year and to reach scale commercialisation and volume sales "in the near term" (近期). Both are directional statements without committed dates.

Named target applications: AI phones, AI PCs, AI NAS appliances, and cloud-side "token factories" — that last one being inference-serving capacity measured in tokens rather than FLOPS. The company says it is working with memory vendors, large-model companies, phone and PC OEMs, and server and cloud providers.

What to watch

Three things will determine whether 3D-CIM matters in practice. Whether a published datasheet appears with absolute throughput and power numbers. Whether the software stack can ingest a standard ONNX or PyTorch model without a bespoke toolchain — this is historically where CIM startups fail. And whether the mature-node claim translates into supply continuity that a five-to-ten-year product lifecycle can depend on.

The RISC-V angle here is the quiet one: open-standard control planes are becoming the default for accelerator designs that need programmable orchestration without ISA licensing friction. That is a supply-chain and cost argument, not a performance one, and it is worth making on its own merits.

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com