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RISC-V MCU

Nuvoton NPCR1 OpenTitan RISC-V Secure MCU Lands in Antmicro's Renode Simulation Framework

2026-09-09 5 min read EN
RISC-V MCU

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Status: DRAFT — not published Date: 2026-09-09 Category: RISC-V MCU Tags: Nuvoton NPCR1, OpenTitan, Earl Grey, Renode, root of trust, FIPS 140-3, Common Criteria, Zephyr Meta description: Nuvoton's NPCR1 OpenTitan RISC-V secure MCU is simulatable in Antmicro's Renode, targeting FIPS 140-3 Level 1 and Common Criteria PP0084. Reading time: ~5 min

Simulation first, silicon second

On 7 September 2026, Nuvoton Technology (Hsinchu, Taiwan) and Antmicro (Gothenburg, Sweden) announced support for Nuvoton chips inside Renode, Antmicro's open-source simulation framework. The focus part is the NPCR1, described by both companies as the first production-ready OpenTitan silicon — a low-power secure microcontroller built on the OpenTitan Earl Grey design and, this time, built around a RISC-V core rather than the Arm Cortex-M4 used in Nuvoton's earlier Chromebook EC parts.

The practical consequence is straightforward: firmware teams can start writing, testing and debugging RoT code before hardware samples exist.

What the NPCR1 is aimed at

Per the announcement, the NPCR1 was developed with the lowRISC CIC inside the OpenTitan project and is dedicated to root-of-trust applications, while remaining usable for other security use cases. Stated characteristics:

Nuvoton's own product page lists the part family as NPCR1xxxxxBX, status Mass Production, with VFBGA81, WFBGA69 and UFBGA63 package options, RoHS compliance, a 0–70 °C operating range, EAL5+, and protection profile PP0084.

Note the phrasing "targeting." The announcement states certification targets, not certifications achieved. If your procurement process needs a completed certificate, that is a question for Nuvoton directly.

Renode coverage and what runs on it

Renode already models OpenTitan, and the Earl Grey platform in Renode includes blocks such as KMAC, CSRNG and the OpenTitan Big Number Accelerator (OTBN) alongside standard peripherals. Antmicro's pitch is that this existing work, plus a library of reusable building blocks, is what let NPCR1 support land quickly.

Beyond simulation, Antmicro points to:

A useful architectural caution

It is tempting to copy the OpenTitan Earl Grey reference datasheet into an NPCR1 spec table. Do not. The published Earl Grey reference design documents an RV32IMCB Ibex core — 3-stage pipeline, single-cycle multiplier, 4 KiB 2-way instruction cache, ePMP, PLIC, U/M modes, dual-core lockstep, 2 × 512 KiB eFlash, 128 KiB SRAM, 100 MHz core domain and 24 MHz peripheral domain.

Nuvoton's NPCR1 is described as using a custom RISC-V core, and Nuvoton has not published an NPCR1 datasheet with register-level detail in the sources reviewed here. The Earl Grey numbers describe the open reference design, not necessarily the shipped commercial part. Treat them as adjacent context, not as NPCR1 specifications.

Context: this is not Nuvoton's first Renode part

The relationship predates this announcement. In early 2024, working with the Google ChromeOS team, Antmicro added the NPCX9 — an Arm Cortex-M4-based Nuvoton part used in Chromebook products — to Renode, covering UART, SPI, the ITIM32 timer, the TWD module, the MTC timer and parts of the Nuvoton Cryptographic Library. Initial support for NPCX7 and NPCX4 followed.

That history matters for a sourcing decision: Nuvoton has a track record of keeping simulation support maintained across a product line rather than shipping a one-off demo.

Why this matters for teams evaluating secure silicon

Three things stand out from an engineering-procurement angle:

  1. De-risked bring-up. RoT firmware is the hardest code to iterate on once silicon is fixed. Simulation-first support compresses that loop.
  2. Transparent design lineage. OpenTitan is Apache-2.0 licensed and independently auditable. For buyers whose risk model values inspectability and multi-source availability over a single vendor's assurance, that is a concrete property, not a marketing claim.
  3. Honest maturity signals. The announcement is about tooling availability. It does not publish throughput, power, die area or certification completion dates.

Ran Klier, OpenTitan Project Manager at Nuvoton, framed the tooling as the point: simulation-based testing is what improves security across complete software-hardware systems. Michael Gielda, Antmicro Co-Founder and VP Business Development, described the goal as making commercial-grade RISC-V silicon available in Renode for rapid development and comprehensive testing.

Not disclosed in the sources used here: NPCR1 clock frequency, memory sizes, process node, power figures, pricing, lead times, and confirmation that FIPS 140-3 or Common Criteria certification has been completed rather than targeted.

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com