RISC-V Software

Qwenputer: a RISC-V CPU Compiled into the Weights of Qwen3.5, with Gated DeltaNet State as RAM

📅 2026-10-31 ⏱ 11 min read 🔗 Source: divagr18/qwenputer (GitHub, README f07a0b2) + HF model cards

Every large language model hits the same wall: it predicts tokens, it does not compute. Ask for a twenty-digit product and the best-case outcome is a pattern match from training, not an arithmetic result, which is why production stacks bolt on Python interpreters and calculator tools. A project that climbed Hacker News this week takes the opposite exit. Qwenputer, by developer Divyansh Agrawal, puts a complete, deterministic 32-bit RISC-V CPU inside the weights of Qwen3.5-4B — not as a plugin, not as a sandbox, not behind a tool call. The model is the computer.

The ISA choice is the quiet headline. Of all instruction sets that could have been compiled into a neural network, the author picked RV32IM with the Zba extension and a bignum coprocessor, and validated it against the official riscv-tests suites. An open ISA with an exact, freely licensed test suite turns out to be exactly what you want when the "hardware" is a stack of attention heads and the acceptance criterion is bit-exact agreement with a reference machine.

Honesty note. Everything below is read from the primary sources: the divagr18/qwenputer GitHub repository (README at commit f07a0b2, updated 30 October 2026), its experimental/riscv/docs/rv32.md design document, and the author's benchmark tables as echoed by coverage on 30 October. Qwenputer is an experiment, not a product — the author says so directly. Where a number is author-reported rather than independently reproduced, the text says so.

What Actually Got Compiled

The repository's history tells the story in three steps. On 19 October 2026 the first public version compiled a CHIP-8 machine into Qwen3.5-4B: a CPU, a big-number arithmetic library and its memory, written as transformer layers (~0.7M nonzero weights; the merged checkpoint grew from 9.3 GB to 14.65 GB, the extra almost entirely zeros). Between 22 and 23 October the RISC-V version landed under experimental/riscv/ with a quickstart, docs and a chat driver. On 30 October the README gained an in-weights NPU section, as media coverage (IT之家, Hacker News, where the thread reached ~681 upvotes) pushed the project into the mainstream.

The RISC-V machine is 11 transformer layers placed in front of Qwen's own 32. None of their weights are learned: a compiler computes every one, turning a circuit description of the CPU into attention heads, feed-forward units and DeltaNet heads. Qwen's original weights are untouched, and the model still loads as a stock Qwen3_5ForCausalLM. The interface is a clever piggyback: Qwen3.5 was already trained to emit <tool_call> blocks, so the model writes one for a calc tool exactly as it would for a real tool — but nothing outside the model ever runs it. The computer layers read the call, execute it on the RISC-V CPU, and the model itself writes the <tool_response>, digit by digit. No runtime, no sandbox, no tool executor.

git clone https://github.com/divagr18/qwenputer && cd qwenputer/experimental/riscv && uv sync --extra hf
hf download divagr1925/Qwen3.5-4B-Qwenputer --local-dir qwenputer-rv
uv run python -m chipformer.rv.chat qwenputer-rv --firmware tests/data/rv/calc-bridge.elf \
    --ask "Use calc: what is 123456789 * 987654321?"

One caveat is load-bearing: a small driver called RvChat boots the CPU by loading its firmware into the DeltaNet state after the prompt, and keeps the CPU's trace tokens out of Qwen's layers while decoding. A plain generate() call does not work yet. Every generated token still comes from the weights — the driver only manages state, it does no arithmetic.

Gated DeltaNet as Exact RAM

The memory trick is the part that generalizes, and it needs no new layer type. Qwen3.5 mixes full attention with Gated DeltaNet layers — a linear-attention variant where each head carries a fixed-size state matrix updated at every token by the gated delta rule. Normally that state is a lossy, fading summary of context. The author noticed that at the extremes it becomes something much stronger:

Mechanism	Setting	Effect
Gate `α` = 1	Gate held open	Nothing fades; state persists exactly
Write strength `β` = 1	Full-strength writes	Each write fully replaces the target
One-hot key	Key selects one row	Every update overwrites exactly one row — a RAM write
One-hot query	Query reads one row	Returns exactly that row — a RAM read
Gate `α` = 0	Closed for one token	Wipes a whole head (used to clear the CHIP-8 screen)
Gate `α` = ½	Per-step halving	Head decays geometrically — used as a counter

The layout on top of that is engineering, not research: the low bits of an address choose the head, the remaining bits choose the row, each row stores one byte as bits, and each key head drives two value heads to double capacity. Registers, program counter and call stack each get heads of their own. Because writes arrive through the token stream, the token trace is the machine's execution log — an ADDR token names the row, the following VAL token carries the value, and STEP ends the instruction.

Verification: the Numbers That Matter

A CPU made of attention heads is only interesting if it is exact. The author's evidence, as reported in the repository docs:

Passes the official riscv-tests suites and matches QEMU behaviour.
~230,000 output positions replayed through a reference model of the machine with zero mismatches.
Reported ~18 million instructions of free-running execution with zero errors (author-reported; seconded by IT之家 and other coverage on 30 October).
Qwen's normal text behaviour is unchanged: KL divergence 6e-4 against a noise floor of 5e-4 — the computer layers do not degrade the language model they live in.

On the arithmetic benchmarks that motivated the project (greedy decoding, 40 problems per set, from the author's tables):

Benchmark	Base Qwen3.5-4B	Qwen + Python tool (host)	Qwenputer
Long multiplication (DeepMind set)	55.0%	—	97.5%
Big division (DeepMind set)	72.5%	95.0%	97.5%
Multi-step multiply/divide	—	—	100%
NUPA long-integer set	48.6%	100%	100%

The instructive column is the middle one. A base 4B model with a real Python interpreter attached scores 95% on division — the tool chain itself is imperfect. The in-weights CPU matches or beats it with no external runtime at all, because the computation is a compiled circuit rather than a stochastic predictor plus glue code.

Why RISC-V specifically. An in-weight CPU must be verified against something, and "something" has to be a complete, public, license-free specification with an executable test suite. That is precisely what riscv-tests provides for RV32IM. Compiling a proprietary ISA into weights would leave the acceptance criterion undefined — the same argument the ecosystem makes for silicon, made at a stranger layer of the stack.

An In-Weights Filesystem

The same DeltaNet addressing scheme extends to persistent storage. The experimental rv-store branch (model: Qwen3.5-4B-Qwenputer-Filesystem) adds five tools next to calc: put, append, get, list, delete. File names hash to a slot in a directory kept in DeltaNet state (a lookup costs two or three trace tokens instead of a scan); file text lives in other heads, eight tokens to a row. Capacity: up to 512 files, about 53,000 tokens of text. Save the heads at the end of a conversation, reload them at the start of the next one, and the files are still there — memory that survives the chat window, computed by the same weights that answer the questions.

Benchmark	Base Qwen3.5-4B	Qwenputer Filesystem	Python tool (host)
Multi-session recall (90 questions)	7.8	83.3	78.9
Facts that changed in a later session (30 questions)	3.3	90.0	83.3

Beating a host-side Python memory tool on its own turf — from inside the model — is the result that most surprises people. It should not, once the mechanism is clear: exact storage plus exact recall is what a memory cell does, and the model now contains real ones.

An In-Weights NPU, Too

The 30 October README update extends the same idea to neural computation. The npu branch (model: Qwenputer-npu) adds three instructions to the RISC-V core — VDOT (multiply 8 int8 activations by the next 8 int4 weights, accumulate), SMAQA (four signed byte products, as in the RISC-V P extension) and WB (set the weight-memory base) — plus a weight memory holding 261,120 int4 weights in DeltaNet heads, loaded from the program. Each is one instruction and one trace token, computed exactly by the compiled layers.

The demo: Karpathy's stories260K, a 260K-parameter Llama, runs as a C program on the CPU inside Qwen and writes its stories. Its weights are data in CPU memory, not compiled into the checkpoint, so any model that fits runs the same way:

Build of stories260K	Trace tokens per story token
Plain C, int8 weights	2,430,000
VDOT + SMAQA, int4 weights	225,000

The int4 build is ~10.8× cheaper in trace tokens — matrix arithmetic through native multiply-accumulate instructions instead of software loops over bignum routines. A fused executor runs the CPU at about 5,500 trace tokens per second on an L4, which still puts a story token at roughly 41 seconds. This is a proof of mechanism, not a throughput claim.

The Costs, Stated Plainly

The project is refreshingly honest about what it costs:

Checkpoint size: the RISC-V model is 18.8 GB, roughly double the base model — the extra layers carry uniform width and the padding is almost all zeros, but you download every zero.
Speed: each CPU instruction costs several decoded trace tokens. The Triton executor runs ~3,200 trace tokens/s on an L4; a calculation that takes a GPU nanoseconds takes the model seconds.
Bootstrapping: the RvChat driver is required; plain generate() does not boot the firmware yet.
Scope: it is an experiment — the author's own framing — with the stated next steps being a python() tool that runs MicroPython in-weights and a faster CPU.

How to Read This

Three observations.

First, "compiled, not trained" is the load-bearing distinction. A learned circuit inside a network would be one more learned component with statistical behaviour. A compiled one has an author, a source language (a circuit description), and a verification target — the same relationship RTL has to a spec. The 230,000-position replay with zero mismatches is meaningful precisely because the weights were written, not fit. The author also points at the security-relevant direction: exact control over RNN state makes the model a testbed for monitorability research (an in-weight monitor the model cannot switch off), which the repository's research/hidden-reasoning directory is already probing.

Second, the RISC-V choice did real work here. riscv-tests, QEMU as a reference semantics, and a small, orthogonal ISA made both the compilation target and the acceptance criterion well-defined. This is the ISA's verification culture — built for silicon IP exchange — repurposed for a medium nobody had compiled a CPU into before. The ecosystem's habit of publishing exact test suites is a bigger asset than it looks.

Third, keep the scale in view. This is a 4B-parameter model doing arithmetic in seconds, hosted on a 24 GB GPU. Nobody is replacing a calculator. What the project demonstrates is that weights can hold deterministic machinery, exactly and verifiably, with the host model's language behaviour statistically unchanged — and that the machinery can be specified in an open ISA that anyone can audit. Where that goes next (faster executors, tighter encodings, real tool integration) is the author's roadmap; what is already true today is the demonstration itself.

摘要（中文）

开发者 Divyansh Agrawal 的 Qwenputer 项目把一颗完整的 32 位 RISC-V CPU（RV32IM + Zba + bignum 协处理器）「编译」进 Qwen3.5-4B 的权重： CPU 是加在 Qwen 自己 32 层之前的 11 个 transformer 层，没有任何一个权重是训练出来的，全部由编译器从 CPU 电路描述直接算出；模型原始权重不动，仍按标准 Qwen3_5ForCausalLM 加载。项目 10 月 19 日首发 CHIP-8 版本，10 月 22–23 日上线 RISC-V 版，10 月 30 日 README 新增片上 NPU 章节，同日经 IT之家报道与 Hacker News（约 681 赞）进入大众视野。

核心机制：RAM 用的是 Qwen3.5 自己的 Gated DeltaNet 层状态——把门控 α 置 1、写入强度 β 置 1、key 用 one-hot 向量，每次写入就精确覆盖状态矩阵的一行（RAM 写）， one-hot query 精确读回该行（RAM 读）；α=0 可整头清零、α=1/2 可当衰减计数器。地址低位选 head、高位选 row，每行按位存一个字节；寄存器、PC、调用栈各占独立 head。CPU 通过 Qwen 已训练过的 <tool_call> 格式收指令，全程模型内部执行，无任何外部运行时。

验证与结果（作者报告）：通过官方 riscv-tests 测试套件、与 QEMU 行为一致；约 23 万个输出位置对参考机重放零失配；自由运行约 1800 万条指令 零错误；Qwen 文本行为不变（KL 6e-4，噪声底 5e-4）。算术基准：长乘法 55%→97.5%、大数除法 72.5%→97.5%、NUPA 长整数 48.6%→100%（带 Python 工具的基线也只有 95% 的除法分）。

扩展玩法：① 权重内文件系统（rv-store 分支）——put/get/list/delete/append 五个工具，文件名哈希到槽位，最多 512 个文件、约 5.3 万 token，跨会话可持久化；多会话召回 7.8→83.3（主机 Python 工具仅 78.9），事实变更追踪 3.3→90.0。 ② 权重内 NPU（npu 分支）——新增 VDOT/SMAQA/WB 三条指令 + 261,120 个 int4 权重，Karpathy stories260K 以 C 程序在模型内运行，每 story token 的 trace token 从 243 万降到 22.5 万（约 10.8×）。

代价（作者明说）：checkpoint 18.8 GB（约两倍，多出来几乎全是零填充）；每条 CPU 指令要解码多个 trace token，L4 上 Triton 执行器约 3,200 token/s、融合执行器约 5,500 token/s，大计算要秒级而非毫秒级；需要 RvChat 驱动引导固件，暂不支持裸 generate()。

一句话：项目证明「权重里可以放下可验证的确定性机器」——而选择 RISC-V 不是巧合：开放的 ISA、精确的测试套件（riscv-tests）和 QEMU 参考语义，正好构成了把 CPU 编译进神经网络后唯一可用的验收标准。这是 RISC-V 验证文化在一个全新介质上的复用。MIT 许可，代码与模型全开源。

Кратко (RU)

Проект Qwenputer разработчика Divyansh Agrawal «компилирует» полный 32-битный RISC-V CPU (RV32IM + Zba + сопроцессор bignum) в веса Qwen3.5-4B: CPU — это 11 трансформерных слоёв перед собственными 32 слоями Qwen, и ни один вес не обучен — все вычислены компилятором из описания схемы. Исходные веса Qwen не тронуты, модель грузится как обычный Qwen3_5ForCausalLM. История: 19 октября — версия CHIP-8, 22–23 октября — RISC-V-версия, 30 октября — секция NPU в README и широкое освещение (Hacker News ~681 голос).

Механизм: RAM — состояние собственных слоёв Gated DeltaNet: при α=1 и β=1 one-hot ключ перезаписывает ровно одну строку матрицы состояния (запись), one-hot запрос возвращает её (чтение); α=0 очищает голову, α=1/2 работает как счётчик. Младшие биты адреса выбирают голову, старшие — строку; в строке хранится один байт. Инструкции приходят через обученный формат <tool_call> — всё исполняется внутри модели, без внешних рантаймов.

Проверка (по данным автора): официальные наборы riscv-tests пройдены, поведение совпадает с QEMU; ~230 000 выходных позиций воспроизведены против эталонной машины без единого расхождения; ~18 млн инструкций свободного выполнения без ошибок; текстовое поведение Qwen не изменилось (KL 6e-4 при шумовом пороге 5e-4). Арифметика: умножение 55%→97.5%, деление 72.5%→97.5%, NUPA 48.6%→100% (база с Python-инструментом — только 95% на делении).

Расширения: файловая система в весах (до 512 файлов, ~53 тыс. токенов, персистентна между сессиями: recall 7.8→83.3 против 78.9 у Python-инструмента) и NPU в весах — команды VDOT/SMAQA/WB плюс 261 120 int4-весов: stories260K исполняется как C-программа, стоимость падает с 2 430 000 до 225 000 trace-токенов за токен истории (~10.8×).

Цена: чекпоинт 18.8 ГБ (примерно вдвое больше базы, добавка почти вся нулевая); каждая инструкция CPU — несколько декодированных токенов (~3 200 token/s на Triton, ~5 500 в fused-режиме, на L4), большие вычисления занимают секунды; нужен драйвер RvChat, голый generate() пока не работает. Лицензия MIT, код и модели полностью открыты.

Resumen (ES)

El proyecto Qwenputer del desarrollador Divyansh Agrawal «compila» una CPU RISC-V de 32 bits completa (RV32IM + Zba + coprocesador bignum) dentro de los pesos de Qwen3.5-4B: la CPU son 11 capas transformer colocadas delante de las 32 capas de Qwen y ninguno de sus pesos se entrena — un compilador calcula todos a partir de la descripción del circuito. Los pesos originales no se tocan y el modelo carga como un Qwen3_5ForCausalLM estándar. Cronología: 19 de octubre versión CHIP-8, 22–23 de octubre la versión RISC-V, 30 de octubre la sección NPU en el README y cobertura masiva (Hacker News ~681 votos).

Mecanismo: la RAM es el estado de las propias capas Gated DeltaNet: con α=1 y β=1, una clave one-hot sobrescribe exactamente una fila de la matriz de estado (escritura) y una consulta one-hot la lee de vuelta (lectura); α=0 borra una cabeza entera y α=1/2 funciona como contador. Los bits bajos de la dirección eligen la cabeza, el resto la fila; cada fila guarda un byte. Las instrucciones llegan por el formato <tool_call> ya entrenado — todo se ejecuta dentro del modelo, sin runtimes externos.

Verificación (según el autor): pasa las suites oficiales riscv-tests y coincide con QEMU; ~230 000 posiciones de salida reproducidas contra una máquina de referencia sin ninguna discrepancia; ~18 millones de instrucciones en ejecución libre sin errores; el comportamiento textual de Qwen no cambia (KL 6e-4 frente a un suelo de ruido de 5e-4). Aritmética: multiplicación 55%→97.5%, división 72.5%→97.5%, NUPA 48.6%→100% (la base con herramienta Python solo logra 95% en división).

Extensiones: sistema de archivos en los pesos (hasta 512 archivos, ~53 000 tokens, persistente entre sesiones: recall 7.8→83.3 frente a 78.9 de la herramienta Python) y NPU en los pesos — instrucciones VDOT/SMAQA/WB más 261 120 pesos int4: stories260K se ejecuta como programa C y el coste baja de 2 430 000 a 225 000 trace-tokens por token de historia (~10.8×).

Costes: checkpoint de 18.8 GB (el doble de la base, el extra es casi todo relleno de ceros); cada instrucción CPU cuesta varios tokens decodificados (~3 200 token/s con Triton, ~5 500 en modo fusionado, sobre una L4); los cálculos grandes tardan segundos; hace falta el driver RvChat, un generate() plano aún no funciona. Licencia MIT, código y modelos totalmente abiertos.

Résumé (FR)

Le projet Qwenputer du développeur Divyansh Agrawal « compile » un processeur RISC-V 32 bits complet (RV32IM + Zba + coprocesseur bignum) dans les poids de Qwen3.5-4B : le CPU constitue 11 couches transformer placées devant les 32 couches de Qwen, et aucun de leurs poids n'est appris — un compilateur les calcule tous à partir de la description du circuit. Les poids originaux restent intacts et le modèle se charge comme un Qwen3_5ForCausalLM standard. Chronologie : 19 octobre version CHIP-8, 22–23 octobre la version RISC-V, 30 octobre la section NPU du README et une large couverture médiatique (Hacker News ~681 votes).

Mécanisme : la RAM est l'état des propres couches Gated DeltaNet : avec α=1 et β=1, une clé one-hot écrase exactement une ligne de la matrice d'état (écriture) et une requête one-hot la relit (lecture) ; α=0 efface une tête entière, α=1/2 sert de compteur. Les bits bas de l'adresse choisissent la tête, les autres la ligne ; chaque ligne stocke un octet. Les instructions arrivent via le format <tool_call> déjà entraîné — tout s'exécute dans le modèle, sans runtime externe.

Vérification (selon l'auteur) : les suites officielles riscv-tests sont passées, comportement identique à QEMU ; ~230 000 positions de sortie rejouées contre une machine de référence sans aucune divergence ; ~18 millions d'instructions en exécution libre sans erreur ; le comportement textuel de Qwen est inchangé (KL 6e-4 contre un plancher de bruit de 5e-4). Arithmétique : multiplication 55%→97.5%, division 72.5%→97.5%, NUPA 48.6%→100% (la base avec un outil Python n'atteint que 95% en division).

Extensions : un système de fichiers dans les poids (jusqu'à 512 fichiers, ~53 000 tokens, persistant entre sessions : rappel 7.8→83.3 contre 78.9 pour l'outil Python) et un NPU dans les poids — instructions VDOT/SMAQA/WB plus 261 120 poids int4 : stories260K s'exécute comme un programme C et le coût passe de 2 430 000 à 225 000 trace-tokens par token d'histoire (~10.8×).

Coûts : checkpoint de 18.8 Go (environ le double, l'excédent étant presque tout du zéro) ; chaque instruction CPU coûte plusieurs tokens décodés (~3 200 token/s avec Triton, ~5 500 en mode fusionné, sur une L4) ; les gros calculs prennent des secondes ; le driver RvChat est requis, un generate() nu ne fonctionne pas encore. Licence MIT, code et modèles entièrement ouverts.

Zusammenfassung (DE)

Das Projekt Qwenputer des Entwicklers Divyansh Agrawal „kompiliert“ eine vollständige 32-Bit-RISC-V-CPU (RV32IM + Zba + Bignum-Koprozessor) in die Gewichte von Qwen3.5-4B: Die CPU besteht aus 11 Transformer-Schichten vor Qwens eigenen 32 Schichten, und kein einziges dieser Gewichte ist trainiert — ein Compiler berechnet alle aus der Schaltungsbeschreibung. Die Originalgewichte bleiben unangetastet, das Modell lädt als gewöhnliches Qwen3_5ForCausalLM. Zeitleiste: 19. Oktober CHIP-8-Version, 22.–23. Oktober die RISC-V-Version, 30. Oktober die NPU-Sektion im README und breite Berichterstattung (Hacker News ~681 Upvotes).

Mechanismus: Das RAM ist der Zustand von Qwens eigenen Gated DeltaNet-Schichten: mit α=1 und β=1 überschreibt ein One-hot-Key exakt eine Zeile der Zustandsmatrix (Schreiben), ein One-hot-Query liest sie zurück (Lesen); α=0 löscht einen ganzen Kopf, α=1/2 dient als Zähler. Die unteren Adressbits wählen den Kopf, der Rest die Zeile; jede Zeile speichert ein Byte. Die Instruktionen kommen über das bereits trainierte <tool_call>-Format — alles läuft im Modell, ohne externe Runtime.

Verifikation (laut Autor): die offiziellen riscv-tests-Suiten werden bestanden, das Verhalten stimmt mit QEMU überein; ~230 000 Ausgabepositionen gegen eine Referenzmaschine abgespielt — null Abweichungen; ~18 Millionen Instruktionen Freilauf ohne Fehler; das Textverhalten von Qwen bleibt unverändert (KL 6e-4 gegenüber einer Rauschuntergrenze von 5e-4). Arithmetik: Multiplikation 55%→97.5%, Division 72.5%→97.5%, NUPA 48.6%→100% (die Basis mit Python-Werkzeug schafft nur 95% bei der Division).

Erweiterungen: ein Dateisystem in den Gewichten (bis zu 512 Dateien, ~53 000 Tokens, sitzungsübergreifend persistent: Recall 7.8→83.3 gegenüber 78.9 beim Python-Werkzeug) und ein NPU in den Gewichten — die Instruktionen VDOT/SMAQA/WB plus 261 120 int4-Gewichte: stories260K läuft als C-Programm, die Kosten sinken von 2 430 000 auf 225 000 Trace-Tokens pro Story-Token (~10.8×).

Kosten: Checkpoint 18.8 GB (etwa das Doppelte, der Zuwachs fast nur Null-Auffüllung); jede CPU-Instruktion kostet mehrere dekodierte Tokens (~3 200 Token/s mit Triton, ~5 500 im fused-Modus, auf einer L4); große Berechnungen dauern Sekunden; der RvChat-Treiber ist Pflicht, ein nacktes generate() funktioniert noch nicht. MIT-Lizenz, Code und Modelle vollständig offen.

خلاصه (FA)

پروژهٔ Qwenputer ساختهٔ توسعه‌دهندهٔ Divyansh Agrawal یک پردازندهٔ کامل ۳۲ بیتی RISC-V (‏RV32IM + Zba + هم‌پردازندهٔ bignum) را در وزن‌های Qwen3.5-4B «کامپایل» می‌کند: پردازنده ۱۱ لایهٔ ترنسفورمر پیش از ۳۲ لایهٔ خودِ Qwen است و هیچ‌کدام از وزن‌های آن آموزش ندیده‌اند — کامپایلر همه را از توصیف مدار محاسبه کرده است. وزن‌های اصلی دست‌نخورده‌اند و مدل مانند یک Qwen3_5ForCausalLM معمولی بارگذاری می‌شود. گاه‌شمار: ۱۹ اکتبر نسخهٔ CHIP-8، ۲۲–۲۳ اکتبر نسخهٔ RISC-V، ۳۰ اکتبر بخش NPU در README و پوشش رسانه‌ای گسترده (Hacker News حدود ۶۸۱ رأی).

سازوکار: حافظهٔ RAM، حالت لایه‌های Gated DeltaNet خودِ مدل است: با α=۱ و β=۱، کلید one-hot دقیقاً یک سطر از ماتریس حالت را بازنویسی می‌کند (نوشتن) و پرس‌وجوی one-hot همان سطر را برمی‌گرداند (خواندن)؛ α=۰ یک head را کامل پاک می‌کند و α=۱/۲ مانند شمارنده عمل می‌کند. بیت‌های پایین آدرس head را انتخاب می‌کنند و بقیه سطر را؛ هر سطر یک بایت ذخیره می‌کند. دستورها از طریق قالب آموزش‌دیدهٔ <tool_call> می‌آیند — همه‌چیز درون مدل اجرا می‌شود، بدون هیچ رuntime بیرونی.

راستی‌آزمایی (به گفتهٔ نویسنده): مجموعه‌های رسمی riscv-tests پاس می‌شوند و رفتار با QEMU یکسان است؛ حدود ۲۳۰٬۰۰۰ موقعیت خروجی نسبت به ماشین مرجع بازپخش شده و هیچ ناهمخوانی ندارد؛ حدود ۱۸ میلیون دستور اجرای آزاد بدون خطا؛ رفتار متنی Qwen تغییر نکرده (KL برابر 6e-4 در برابر کف نویز 5e-4). محاسبات: ضرب ۵۵٪→۹۷.۵٪، تقسیم ۷۲.۵٪→۹۷.۵٪، NUPA ۴۸.۶٪→۱۰۰٪ (مدل پایه با ابزار Python فقط ۹۵٪ در تقسیم).

توسعه‌ها: فایل‌سیستم درون‌وزنی (تا ۵۱۲ فایل، حدود ۵۳ هزار توکن، ماندگار میان نشست‌ها: بازیابی ۷.۸→۸۳.۳ در برابر ۷۸.۹ ابزار Python) و NPU درون‌وزنی — دستورهای VDOT/SMAQA/WB به‌همراه ۲۶۱٬۱۲۰ وزن int4: داستان‌های stories260K به‌صورت برنامهٔ C درون مدل اجرا می‌شود و هزینه از ۲٬۴۳۰٬۰۰۰ به ۲۲۵٬۰۰۰ توکن ردگیری برای هر توکن داستان می‌رسد (~۱۰.۸ برابر).

هزینه‌ها: چک‌پوینت ۱۸.۸ گیگابایت (تقریباً دو برابر، افزوده تقریباً همه صفر است)؛ هر دستور CPU چند توکن رمزگشایی‌شده هزینه دارد (~۳٬۲۰۰ توکن/ثانیه با Triton، ~۵٬۵۰۰ در حالت fused، روی L4)؛ محاسبات بزرگ چند ثانیه طول می‌کشد؛ درایور RvChat لازم است و generate() خالی هنوز کار نمی‌کند. مجوز MIT، کد و مدل‌ها کاملاً باز.

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