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RISC-V Datacenter

SemiFive Starts Mass Production of HyperAccel Bertha: A >500 mm² 4nm Inference Accelerator

2026-09-08 5 min read EN
RISC-V custom silicon Samsung Foundry 4nm ASIC LLM inference SemiFive HyperAccel

Table of Contents

An important caveat first

Neither SemiFive's press release nor HyperAccel's public material names the instruction set architecture used in Bertha. We could not confirm that the part contains RISC-V cores. This draft is included because SemiFive is a custom-silicon design house operating in the same supply chain that RISC-V datacenter and inference programmes depend on, and because the manufacturing and contract mechanics below are directly relevant to anyone commissioning custom silicon. Read the performance and architecture figures as what they are: largely vendor-stated, with the ISA unconfirmed.

What was announced

On 8 September 2026, SemiFive announced from Seoul that it has begun mass production of a data-centre AI inference accelerator for HyperAccel, a South Korean fabless company. The accelerator, called Bertha, is fabricated on Samsung Foundry's 4nm process and is SemiFive's first large-scale mass-production programme at that node.

The headline number is physical: die area greater than 500 mm². That is a large die by any standard. As die area grows, power delivery, heat dissipation, packaging and yield all get harder, and yield is what determines unit cost. SemiFive's argument is that it carried the programme through the whole chain — front-end design, verification, packaging, test and volume manufacturing supply — on a turnkey basis.

The company previously disclosed the 4nm SF4X implementation of the Bertha die at the Samsung Advanced Foundry Ecosystem (SAFE) Forum on 29 May 2026.

Schedule slipped two quarters

The development and mass-production contract between the two companies was signed in October 2024, with mass production originally targeted for Q1 2026. Production starting in September 2026 means the programme ran roughly two quarters late, according to The Elec. Delays of this size on a large advanced-node die are normal; it is still worth recording, because anyone planning a custom-silicon schedule should budget for it.

Contract terms disclosed through Korea's Financial Supervisory Service electronic disclosure: the agreement runs through 15 June 2028, with payment staged 10% on signing, 60% on first delivery, 30% on completion. The contract value is undisclosed at the counterparty's request, though The Elec reports it exceeds 10% of SemiFive's 2025 revenue of approximately KRW 121 billion.

SemiFive's production pipeline

Bertha is the third mass-production programme SemiFive has landed in roughly a year:

ProgrammeSegmentProduction start
Hanwha Vision "Wisenet 9" AI ASICSecurity camerasQ3 2025
HPC AI chip, Japanese customerHigh-performance computingQ2 2026
HyperAccel "Bertha"Data-centre LLM inferenceQ3 2026

The shift matters more than any single chip. SemiFive is moving from one-time NRE engagements to recurring production revenue. Company figures: KRW 42.3 billion in new mass-production orders in H1 2026, against KRW 21.2 billion for all of 2025. Quarterly order intake rose 71%, from KRW 15.6 billion in Q1 to KRW 26.7 billion in Q2 2026, with overseas orders accounting for 45% of Q2 bookings. H1 2026 revenue was KRW 94.7 billion, with full-year guidance above KRW 200 billion. CEO is Cho Myung-hyun.

What Bertha is claimed to be

HyperAccel, founded January 2023 by KAIST professor and former Microsoft engineer Joo-Young Kim, markets Bertha as an LPU — a "latency" or "LLM processing unit" — specialised for transformer inference rather than general GPU workloads. Its stated design themes are AI-specialised programmable cores, streamlined dataflow that keeps weights moving toward execution units and reuses parameters across cores, and multi-chip scaling that overlaps communication with computation.

Chinese tech outlet ITHome, reporting on 9 September, published figures attributed to HyperAccel's own materials for the Bertha 500: 768 TFLOPS FP8, support for FP16/8/4 and INT8/4, 256 MB on-chip SRAM, off-chip LPDDR5X at 128 GB or 256 GB, 250 W TDP, dual-slot PCIe add-in-card form factor, and claims of 2× throughput, 19× cost-efficiency and 12× energy efficiency versus an NVIDIA H100. The memory-bandwidth figure of roughly 546 GB/s in that report is ITHome's own inference, not a stated specification. None of these numbers appear in SemiFive's press release and we did not find them on HyperAccel's own site. Treat them as unconfirmed secondary reporting.

HyperAccel is also reported to be closing a Series B of approximately KRW 200 billion at a post-money valuation near KRW 800 billion, with Krafton investing KRW 50 billion. Naver Cloud is named as a potential customer — potential, not contracted.

Why this matters if you are planning custom silicon

Three transferable lessons. First, design-house capacity at advanced nodes is a real constraint; SemiFive's ability to take a >500 mm² 4nm die to volume is the product being sold, not the chip. Second, budget two quarters of schedule slip on a first big-die advanced-node programme. Third, contract structure now carries the risk — staged payments across a multi-year term, with volume tied to the customer's own service ramp rather than a fixed commitment.

For the RISC-V ecosystem specifically, the open question is how much of this custom-accelerator wave ends up on open-standard control planes. SemiFive's public SoC-platform material does not identify its CPU IP vendor, and this announcement does not mention RISC-V at all. That silence is itself a data point.

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com