AMD ROCm 10.0 Runs on the SiFive BigSky SF-2U870: 32 P870-D Cores as a RISC-V AI Host

Published: 2026-09-16 · Category: RISC-V Datacenter · Reading time: ~4 min · Status: DRAFT

What was actually demonstrated

On 15 September 2026, at the AI Infra Summit in Santa Clara, SiFive and AMD showed AMD ROCm running on SiFive's BigSky datacenter development platform. The demonstration ran the Gemma4-E2B LLM using ROCm 10.0, with SiFive Performance P870-D CPUs acting as the head node and AMD Radeon AI PRO R9700 GPUs handling inference offload.

Read the wording in the announcement carefully. SiFive describes it as a demonstration-only system, and AMD's vice president of AI software product management calls it "an early step in enabling developers to explore ROCm-based AI acceleration on RISC-V host platforms." Neither company claimed a supported, shipping product. For an engineering team, that distinction is the whole story: this is a portability proof point, not a procurement option.

BigSky SF-2U870: the published specification

The platform is the SF-2U870, a 2U rackable system that SiFive says is built explicitly for software porting, workload tuning and validation rather than production deployment. The published hardware specification:

SiFive states the platforms are available today, with sales contact as the route to obtaining one. The 64 Gen5 lanes are the part that matters for this specific demo: a GPU offload path is bandwidth-bound at the host interface long before it is compute-bound at the CPU.

Why the host CPU is the hard part

Porting ROCm to a new host architecture is not primarily a compiler exercise. The ROCm stack reaches into PCIe device enumeration, IOMMU and memory-management behaviour, hugepage and pinned-memory semantics, userspace driver ioctls, and the low-level runtimes that move tensors between host and device memory. Any assumption baked in around x86 page-table or cache-coherency behaviour has to be found and fixed.

That is why getting an LLM to run end-to-end — even a 2B-parameter model — is a more meaningful signal than a synthetic kernel benchmark. It means the whole path from model load through host-side buffer management to device submission completed on a RISC-V host.

What "runs" does and does not tell you

The announcement publishes no performance numbers. There is no tokens-per-second figure, no time-to-first-token, no comparison against an x86 or Arm host, and no statement about which ROCm components are enabled versus stubbed. There is also no power, thermal, or rack-density data.

For teams evaluating RISC-V for AI infrastructure, the practical read is that the software-portability question has moved from "can it be done" to "how fast is it, and how much of the stack is covered." Those are the two questions the next round of disclosure has to answer.

Ecosystem context

SiFive's wider datacenter pitch rests on the platform being RVA23-compliant and supported by mainstream enterprise Linux. Industry coverage of the BigSky launch has cited Ubuntu 26.04 LTS and RHEL 10 support and an NVIDIA CUDA port, and SiFive's datacenter SVP frames the AMD work as part of making hyperscalers able to run advanced AI workloads on RISC-V without a custom software stack.

Treat the CUDA and distribution-support claims as reported rather than confirmed: they appear in secondary coverage, not in this 15 September SiFive release. Verify them against Canonical, Red Hat and NVIDIA material before you plan around them.

What is not disclosed

Performance of any kind. Power draw. Pricing. Lead time. Which ROCm libraries are functional. Whether the P870-D head node was running a vendor or upstream kernel. Whether the Radeon AI PRO R9700 required any firmware or driver change to work on a RISC-V host — the announcement does not say, and that is exactly the kind of detail that determines how reproducible the demo is.

Engineering takeaway

If you are assessing RISC-V for AI hosts, this demo is worth tracking but not worth planning around yet. The credible near-term use for a BigSky-class system is what SiFive itself says it is for: porting, profiling and validation — de-risking a future custom-silicon decision. Ask SiFive and AMD for the two missing artefacts, a supported-component list and a benchmark, and treat the answers as the real milestone.

Sources

• SiFive press release — "SiFive and AMD Collaborate to Optimize AMD ROCm on RISC-V Datacenter Servers", Santa Clara, 2026-09-15 — https://www.sifive.com/press/sifive-amd-rocm-riscv-datacenter-servers
• NVIDIA AI Infra Summit 2026 event page (confirms summit dates 15–17 September 2026, Santa Clara Convention Center, and a 16 September panel including Matt Langman of SiFive and Madhu Rangarajan of AMD) — https://www.nvidia.com/en-us/events/ai-infra-summit/

Verification notes

• All figures (32 × P870-D @ 2.0 GHz, 256 GB DDR5-5600, 4 × PCIe Gen5 x16 + Gen3 x4, 2 × 7.68 TB U.2 NVMe, 10/25 Gb OCP 3.0 NIC, ROCm 10.0, Gemma4-E2B, Radeon AI PRO R9700) are quoted verbatim from the official SiFive press release dated 15 September 2026. No numbers were inferred or estimated.
• Storage discrepancy flagged and resolved in favour of the official source. Secondary aggregation sites covering the BigSky launch have stated 3.84 TB NVMe. The SiFive release says 2 × 7.68 TB. The official figure is used here; the aggregator figure is noted only to record that a conflict existed.
• The Ubuntu 26.04 LTS / RHEL 10 / CUDA claims are explicitly attributed to secondary coverage in the body and are not in the 15 September SiFive release. They are marked as requiring independent verification.
• Not disclosed and therefore not estimated: performance, power, price, availability, ROCm component coverage, kernel version, driver/firmware changes.
• The phrase "demonstration-only system" is SiFive's own wording and is reproduced because it materially limits the claim.
• Political framing deliberately avoided; the draft uses open-standard and multi-source-supply positioning only.