SpacemiT K1 and K3: What Landed Upstream in August 2026 — Kernel, Triton, llama.cpp and Toolchain

Why an upstream report is the most useful kind of RISC-V news

Chip announcements are easy to fake; merged patches are not. SpacemiT publishes a monthly upstream-progress report on its developer forum, and the August 2026 edition (posted in early September 2026) is a dense, link-verifiable account of what actually moved into public trees for the K1 and K3 RISC-V AI SoCs.

For engineers, this document is more decision-relevant than a spec sheet: it shows which subsystems still depend on out-of-tree vendor patches.

Linux kernel: K1 stabilising, K3 still filling in

K1 — merged:

• Milk-V Jupiter CPU scaling (partial patch set)
• Maximum CPU core voltage fix across K1 boards
• Thermal shutdown and registration-order fix (thermal tree)

K1 — in review:

• CPU scaling for three K1 boards
• USB2 PHY Kconfig fix and default-enable
• RISC-V defconfig enabling DWC3 and the K1 thermal sensor

K3 — merged:

• Ethernet PHY dt-schema fix
• I2S controller DTS nodes
• USB controller and USB PHY nodes (partial)
• I2S clock topology and divider fixes
• SpacemiT pinctrl pinconf validation (pinctrl tree)
• ASoC redundant error-log cleanup (sound.git)
• K1/K3 I2S MAINTAINERS entry
• ASoC: publish only DMA-backed DAI streams
• RTC regmap_test_bits error handling (RTC tree)

K3 — in review:

• PCIe device node
• UFS host controller (v3)
• Display support (v2)
• Clock and reset support (v1)
• PLL5/PLL8 1.8 GHz rates
• PDMA extended DRCMR base fix
• M-level IMSIC guest properties and num-guest-ids fixes
• Pico-ITX Bluetooth and WiFi
• OrangePi RV2 DTS node ordering
• Sensylink CTF2301 and K3 CoM260 support
• SpacemiT reset controller MAINTAINERS entry

Also in flight: RVA23U64 hwprobe support with Zic64b for K1 and K3, from the Qualcomm OSS tree — the same hwprobe mechanism that lets userspace discover RVA23 features at runtime instead of at compile time.

On the firmware side, OpenSBI support for the SpacemiT K3 platform was updated to v3, with expected-trap handling, hart init and RV64-only build revised after review.

The read: K1 is in maintenance mode — voltage, thermals and scaling, which is what you fix on a shipping part. K3 is still landing peripherals. Display, UFS, PCIe and clock/reset being in review rather than merged is the key line for anyone planning a K3 product.

AI software stack: Triton lands in FlagTree

The most consequential item is not a kernel patch. The Triton backend for SpacemiT hardware was merged into FlagTree, the FlagOS Triton fork, under third_party/spacemit (PR #933). Triton is the Python DSL that most modern inference kernels are now written in; having a vendor backend in a public tree rather than a private SDK is the difference between a portable model-serving stack and a vendor lock-in trap.

On the inference side, SpacemiT's llama.cpp fork gained Qwen3-ASR multi-request speech recognition. llama-server now exposes an OpenAI-compatible interface with multi-request speech recognition, concurrent audio encode/decode, continuous batching and dynamic scheduling — the continuous-batching piece being what makes concurrent ASR usable on a fixed memory budget.

Toolchain and runtime: the unglamorous half

This is where the report is most useful and gets least attention:

• riscv-gnu-toolchain: LLVM Polly enabled (#1880), LLVM_ASMFLAGS_FOR_TARGET introduced (#1887), GDB upgraded to gdb-17.2-release (#1895), Flang CI job limits applied across all OS versions (#1896), glibc upgraded to 2.44 (#1897)
• box64: a large batch of RV64 dynarec fixes and opcode additions — HADDPS NaN handling, RDTSC/RDTSCP, ROUNDPD qNaN, ANDN/BZHI without Zbb, VMOVDQU, ADCX, VBROADCAST variants, VMOVMSKPS, PHSUBD/PEXTRB and VPBROADCAST[B/W/D/Q] — plus ELF loader support for versioned data symbols and a set of use-after-free fixes
• OpenOCD: hart-index uniqueness validation within a debug module; dcsr cetrig control
• V8 (RISC-V backend): eight fixes including atomic-store fence ordering, register-allocation bugs, Smi int32 checks under pointer compression, and Liftoff constant storage by value width
• riscv-tests: DCSR.MPRVEN test added; dscratch* registers ignored in DisconnectTest
• felix86: x86_64 getdents implemented on top of getdents64; chipStar: promoteInt test uses resolved LLVM_SPIRV; llvm-test-suite: gobmk -fwrapv-pointer fix

The box64 and V8 entries matter commercially: they are what let x86-64 Linux binaries and a modern JavaScript engine run on RISC-V at all. Every dynarec opcode and fence-ordering fix is a compatibility improvement you inherit for free.

Practical takeaways

1. Judge by the merged list, not the datasheet. If your product needs K3 display or UFS, budget for carrying vendor patches.
2. Triton-in-FlagTree is a portability win. Model work written in Triton targets SpacemiT hardware through a public fork, not a closed SDK.
3. Toolchain currency is good. glibc 2.44 and GDB 17.2 are recent, which lowers the "stale vendor toolchain" risk.
4. RVA23U64 hwprobe is the one to watch. Runtime feature discovery is what lets one distribution image span K1 and K3.

Sources

• SpacemiT community forum, "进迭时空 Upstream 进展 – 2026 年 8 月" — https://forum.spacemit.com/t/topic/1623
• FlagTree (FlagOS) Triton fork, PR #933 — https://github.com/flagos-ai/FlagTree/pull/933
• SpacemiT llama.cpp fork — https://github.com/spacemit-com/llama.cpp
• riscv-gnu-toolchain PRs #1880 / #1887 / #1895 / #1896 / #1897 — https://github.com/riscv-collab/riscv-gnu-toolchain
• OpenSBI K3 platform support v3 — https://lore.kernel.org/all/20260827-spacemit-k3-v3-0-5d8dbb68539d@linux.spacemit.com/
• RVA23U64 hwprobe + K1/K3 Zic64b — https://lore.kernel.org/all/20260812-rva23u64-hwprobe-v2-v6-0-c985af3256b8@oss.qualcomm.com/

Verification notes

• Every patch, PR and version number above is quoted from the SpacemiT forum post, which links the original mailing-list threads and pull requests. No figure has been estimated.
• The forum post summarises August 2026 activity and was published in early September 2026; the exact publication timestamp is not quoted because the page did not render a date during retrieval.
• Subsystem names are quoted as written in the source ( "M-level IMSIC", "Pico-ITX", "Sensylink CTF2301", "CoM260" ). Spelling variants such as "Sensylink" are reproduced verbatim.
• Not disclosed in the source: K1/K3 core counts, clock frequencies, TOPS figures, process node, power envelopes, board pricing, and target merge windows for any in-review patch set. None of these are estimated here.
• Statements about what is "merged" versus "in review" reflect the state as of the report's publication and may have changed since.