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RISC-V Datacenter

YiXing Intelligence Raises ¥1.5B to Scale Its Epoch RISC-V Cloud AI Chip and ELink Superpod

2026-09-07 7 min read EN
RISC-V Datacenter

Table of Contents

What was announced

YiXing Intelligence (奕行智能), a Beijing-area developer of RISC-V cloud AI compute chips, announced the close of a ¥1.5 billion (RMB) Series B round. The company said the proceeds will go to four things: accelerating mass production and commercialisation of its Epoch product series, R&D on next-generation flagship products, building out a hardware–software co-design ecosystem, and expanding into global markets.

For a RISC-V audience, the interesting part is not the round itself. It is that the round is explicitly attached to a system-level product — an AI superpod built on Epoch silicon and a proprietary interconnect called ELink — rather than to a standalone accelerator card.

Who put the money in

The round was jointly led by four Beijing-affiliated funds:

Existing shareholders also increased their positions: HeLi Capital, Boqii Venture Capital, Saiyi Industry Fund, Longjiang Fund, Qingtancapital and JiuKun Venture Capital. The amount was not broken out per investor.

What Epoch is, according to published reports

Epoch is described as a cloud-side, large-scale AI compute chip built on the RISC-V ISA. Reporting from WAIC 2026 attributes the following to the company:

Treat all of the above as vendor-stated. No clock frequency, core count, peak TOPS/FLOPS, process node, memory type or power envelope has been published, and none should be inferred.

The superpod: 32 to 128 cards per rack

The system-level claim is the part that changes the evaluation. Reporting describes the superpod as:

Two vendor-quoted design figures appear in coverage — interconnect hardware cost reduced by about 80%, and latency in the hundreds of nanoseconds. These are engineering targets stated by the company, not independently measured benchmarks, and one of the sources covering them flags them as such. Do not size a deployment on them.

Epoch chips, accelerator cards and associated hardware are reported to be in mass production and batch delivery, with customers named by sector rather than by name: internet, telecom, finance and energy.

Why the software stack matters more than the silicon here

The most checkable claim in the whole package is software. Coverage states the stack is natively compatible with PyTorch, vLLM and SGLang. That is the actual gate for a cloud AI accelerator: if the serving path works without a private fork, migration cost drops to whatever the operator's own kernel tuning costs. If it does not, the silicon is irrelevant regardless of its peak numbers.

For RISC-V specifically, this is the same pattern that has played out in the server space with RVA23 and enterprise Linux: the architecture becomes viable when mainstream frameworks treat it as a target, not when a datasheet posts a competitive TOPS figure.

What is not disclosed

Nothing below has been published in the sources retrieved, and none of it is estimated here:

Sources

Verification notes

Open RISC-V — RISC-V Silicon & Development Board Store — open-riscv.com