First Mass-Produced RISC-V AI Supernode Goes Live: EVAS Epoch in an Operator Data Center

Most RISC-V datacenter news is about chips: a new core, a new accelerator, a new tape-out. This story is one level up. On September 18, 2026, China-based EVAS Intelligence (奕行智能) announced a new financing round of nearly RMB 2 billion at a reported post-money valuation approaching RMB 15 billion — and the reason investors are paying up is not a datasheet. It is a deployed system: the company's 64-node RISC-V AI supernode, built on its Epoch cloud AI chips, has been running in an operator data center in Shijiazhuang, Hebei — which trade press describes as the first mass-produced RISC-V supernode and the industry's first production orthogonal backplane-free cluster of this type.

The 90-Day Path: Launch → Deployment → New Capital

The timeline matters because datacenter silicon routinely takes years between launch slides and production racks. Here the sequence compressed to roughly a quarter:

The Deployed System: 64 Nodes, No Backplane

The deployed cluster is a 64-node orthogonal backplane-free supernode. Each node carries an E200-L liquid-cooled OAM module built around an Epoch chip, for 64 Epoch chips in the fabric. According to the company, the interconnect delivers 100-nanosecond-class low latency between chips — a vendor-quoted figure — and the system's defining software trick is distributing multiple expert routes across all 64 chips so that Mixture-of-Experts (MoE) models can use the whole fabric as one expert-parallel domain, raising inference throughput.

Why "backplane-free" is the interesting part

Conventional AI racks hang accelerator cards off a copper backplane or a cable mesh that must carry every scale-up hop through a connector layer. An orthogonal backplane-free design instead places boards so their interconnect endpoints face each other directly, removing the midplane hop entirely. The engineering motivation is signal integrity and hop latency: every connector is a discontinuity, and at the hundreds-of-gigabit speeds a scale-up fabric runs, discontinuities cost margin, power, and nanoseconds. WAIC coverage quoted the company's design targets at roughly 80% lower interconnect hardware cost and hundreds-of-nanoseconds latency — targets, not independent measurements.

The concept is not unique to EVAS — several hyperscaler and switch vendors have shipped or proposed orthogonal direct-connect topologies — but applying it to a mass-produced, commercially deployed RISC-V system is the part that has no precedent, if the company's characterization holds.

MoE expert-parallelism across 64 chips

Modern large models increasingly use Mixture-of-Experts layers, where each token activates only a few of many expert sub-networks. That creates a scheduling problem: experts must live somewhere in the fabric, and every token needs fast access to the right one. Two deployment styles exist — keeping experts local and paying in data movement, or distributing experts across the scale-up domain and paying in latency. EVAS's stated approach spreads multiple expert routes across all 64 Epoch chips, which only pays off if chip-to-chip latency is low and uniform — hence the emphasis on the ~100 ns-class interconnect figure. The same logic extends to PD (prefill/decode) disaggregation, where prefill-heavy and decode-heavy stages run on separate chip groups; the company claims its next-generation supernode lifts PD-disaggregated inference performance by more than 10× (vendor claim, see below).

The Epoch Chip: What Is Actually Public

EVAS remains disciplined about what it publishes — which means the verifiable list is short. What the company has stated across its announcements:

The Money: ~RMB 2B New Round at ~RMB 15B Valuation

The September 18 round is the third capital event for the company this year, and its composition says something about where RISC-V datacenter money is coming from:

Two details stand out. First, Tongfu Microelectronics — one of the world's larger semiconductor assembly-and-test houses — is on the list, which is the kind of investor you want when your chip is in volume production rather than on a roadmap. Second, the round follows an operator deployment rather than preceding it; the capital is scaling a shipped system, not funding the first rack.

What's Next: Gen-2 Silicon Already Taped Out

The company states its next-generation cloud AI chip has completed tape-out, with compute and interconnect performance "several times" the first generation, and that pairing it with second-generation supernode systems raises PD-disaggregated inference performance by more than 10×. The cadence is described as one chip generation per year, with a full-stack layout spanning chip, interconnect, software, and cluster system — the idea being that customers buy workload-fitted deployments rather than bare accelerators.

As always with vendor roadmaps: treat the multipliers as targets. What is checkable is the cadence itself — gen-1 in production, gen-2 taped out, annual rhythm — and each future generation will be verifiable the same way this one was: by whether racks ship.

Why This Matters for RISC-V

• The ISA argument just moved up a level. Until now, the strongest RISC-V datacenter evidence was chip-level: RVA23-compliant server CPUs (SiFive, Ventana, SpacemiT), vector-core accelerators (Axelera). A 64-chip system-level deployment with a custom interconnect and a production operator tenant is a different class of proof — the ISA carried the compute and the platform software around it.
• Custom extensions are doing real work. EVAS's stack layers a proprietary matrix extension and the VISA virtual ISA on top of base RISC-V + RVV — the same "open base + proprietary acceleration" pattern Axelera, and Andes (ACE), and SpacemiT (IME) all use. The base ISA keeps the toolchain, kernel, and framework ports portable; the extensions carry the performance.
• MoE economics reward open-ISA fabrics. Expert-parallel inference is latency-bound and fabric-bound, not ISA-bound. If a RISC-V-based fabric hits competitive latency at competitive cost, the ISA question stops mattering to the buyer — which is exactly the situation the open-ISA ecosystem has been working toward.
• Watch the framework layer. The claim that matters most long-term is EVACA's compatibility with mainstream serving frameworks (PyTorch/vLLM/SGLang, per WAIC coverage). Framework-native RISC-V targets are what turned RVA23 server silicon into a porting destination; the same will decide whether Epoch stays a single-vendor story or becomes a platform others build on.

Bottom Line

A RISC-V AI supernode is no longer a conference demo. Sixty-four Epoch chips are liquid-cooled, interconnected, and serving MoE traffic in a commercial data center, and a ~RMB 2B round at a ~RMB 15B valuation is now underwriting the next generation. None of the headline numbers — 100 ns interconnect, first-tier throughput, 10× PD gains — are independently verified, and the undisclosed list (TOPS, node, memory, benchmarks) is still long. But the deployment itself is the milestone: the industry's first mass-produced RISC-V supernode went live roughly ninety days after it was announced. The next checkpoint is gen-2 silicon and whether the second rack follows the first as quickly.