SiFive + AMD ROCm on BigSky — RISC-V Head Node Gets Its Second GPU Stack

On September 15, 2026, at the AI Infra Summit in Santa Clara, SiFive and AMD demonstrated AMD ROCm 10.0 running on the SiFive BigSky SF-2U870 datacenter development platform. In a demonstration-only system, the companies showed the Gemma4-E2B LLM running with 32 SiFive Performance P870-D RISC-V cores acting as the head node and AMD Radeon AI PRO R9700 GPUs driving the inference offload. The demo ran inside the RISC-V International Pavilion at the summit (September 15–17, Santa Clara Convention Center).

The significance is simple: weeks after NVIDIA showed its CUDA stack running on RVA23 test hardware, a second major GPU vendor has validated the RISC-V head-node path. Both accelerator ecosystems — CUDA and ROCm — have now been demonstrated on RISC-V host CPUs. For an ecosystem that has spent a decade proving itself in embedded and edge designs, this is the clearest signal yet that RISC-V is being taken seriously as AI-infrastructure silicon.

The BigSky SF-2U870 Platform — Official Hardware Specifications

The BigSky SF-2U870 is the 2U rack-mount development platform SiFive announced at Hot Chips 2026, designed explicitly for software porting, workload tuning, and validation testing ahead of custom silicon commitments. Specifications from the official announcement:

The 64 lanes of PCIe Gen5 are the point: they leave room for double-wide GPU slots and dedicated accelerators, which is precisely what makes the platform usable as a head node feeding GPU clusters. The four Gen5 x16 slots are how a Radeon AI PRO R9700 — or, in other labs, an NVIDIA accelerator — gets attached to a RISC-V host at full bandwidth.

What Exactly Ran in the Demo

The strategic framing from both companies was “open source software meets open standard architecture”: Matt Langman (SVP Datacenter, SiFive) positioned ROCm on BigSky as enabling “hyperscalers and developers to run advanced AI workloads seamlessly on RISC-V,” while AMD’s Ramine Roane (corporate VP, AI software product management) called the demo “an early step in enabling developers to explore ROCm-based AI acceleration on RISC-V host platforms.”

Why the Head Node Is the Prize

The head node is the least glamorous and most strategic socket in an AI cluster. It runs orchestration, scheduling, API serving, tool calls, and KV-cache management — the control plane that feeds accelerators their work. NVIDIA itself builds the Vera CPU on a custom Arm core for exactly this duty inside its rack-scale systems. NVLink Fusion exists because some customers want that seat filled by silicon they control.

That is the opening RISC-V is walking through. A merchant RISC-V head node gives hyperscalers and system vendors a way to validate the entire software path — enterprise Linux, drivers, GPU runtimes, cluster tooling — on open-standard silicon before committing to a custom SoC tape-out. Both demos (CUDA, ROCm) target precisely this socket, not the accelerator itself.

CUDA vs ROCm on RISC-V — Where Each Path Stands

Note the asymmetry: NVIDIA’s full C2C/NVLink Fusion integration is explicitly future work, while AMD’s path runs over standard PCIe Gen5 — the same commodity fabric any x86 or Arm server uses today. That makes the ROCm demo, at this stage, the more “ordinary” integration: no custom interconnect, no special silicon, just a standards-compliant RISC-V host with enough PCIe lanes.

The Software Floor Under the Demo: Enterprise Linux on RVA23

None of this lands in a vacuum. The OS layer under BigSky has been maturing all year:

The P870-D Under the Hood

The P870-D is the datacenter-oriented member of SiFive’s Performance P870 family — a 6-wide out-of-order core announced in August 2024, scalable to 32 cores per cluster and up to 256 coherent cores over a CHI bridge. BigSky pairs 32 of them at 2.0 GHz with DDR5-5600, which is a credible baseline for the head-node duty cycle: interrupt handling, network serving, scheduling, and I/O fan-out to GPUs. What SiFive has not published is performance data — no SPEC, no power, no pricing — so the platform proves software compatibility while leaving the competitive question open.

What it does prove, per NVIDIA’s own porting team, is how small the remaining delta is: beyond the RVA23 profile and the RISC-V Server Platform Specification, the extra requirements for a CUDA-class host totaled roughly two pages — principally PCIe coherency and peer-to-peer support. AMD’s ROCm demo lands on the same requirements list. For SoC teams, that is the actionable takeaway: PCIe I/O coherency and P2P are the gate to both GPU ecosystems.

What This Means for the RISC-V Datacenter Road

• Both GPU ecosystems are now open to RISC-V hosts. CUDA and ROCm have both been demonstrated on RISC-V head nodes within months of each other. Vendor lock-in on the host side just got weaker — which is the entire open-standard argument.
• The head node is the entry socket, and it is achievable. It does not require beating x86/Arm on throughput; it requires RVA23 + server platform compliance + PCIe coherency + enterprise Linux + a GPU runtime. BigSky checks all five.
• Development platforms are the Arm playbook, replayed. Arm spent years getting development systems into developers’ hands before hyperscaler custom silicon followed. BigSky (limited quantities, lead customers unnamed) is at exactly that stage.
• The conversion test is 12 months out. SiFive is an IP vendor spending margin to shorten customers’ schedules; the bet pays only if BigSky porting work converts into licensed custom SoCs. Watch for named hyperscaler tape-outs — that is the metric that matters.
• For RISC-V SoC builders: if your roadmap targets AI infrastructure at any level, put PCIe Gen5 I/O coherency and P2P on the mandatory list, run enterprise Linux on RVA23 from day one, and validate against both CUDA and ROCm host requirements — they are now the de-facto specification.

Timeline: From Hot Chips to Two GPU Stacks